Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1993, volume: 12, number: 3

1. Maurizio Damiani, Giovanni De Micheli
   Don't care set specifications in combinational and synchronous logic circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:3, pp:365-388 [Journal]
   
2. Tai A. Ly, Jack T. Mowchenko
   Applying simulated evolution to high level synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:3, pp:389-409 [Journal]
   
3. Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
   An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:3, pp:410-424 [Journal]
   
4. Giovanni Ghione, Fabio Filicori
   A computationally efficient unified approach to the numerical analysis of the sensitivity and noise of semiconductor devices. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:3, pp:425-438 [Journal]
   
5. Victor Martin Agostinelli Jr., Greg M. Yeric, A. F. Tasch Jr.
   Universal MOSFET hole mobility degradation models for circuit simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:3, pp:439-445 [Journal]
   
6. Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham
   VLSI logic and fault simulation on general-purpose parallel computers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:3, pp:446-460 [Journal]