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Maurizio Damiani: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Valeria Bertacco, Maurizio Damiani, Stefano Quer
    Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:391-396 [Conf]
  2. Maurizio Damiani, Giovanni De Micheli
    Recurrence Equations and the Optimization of Synchronous Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:556-561 [Conf]
  3. Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli
    Optimization of Combinational Logic Circuits Based on Compatible Gates. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:631-636 [Conf]
  4. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Maurizio Damiani, Leonardo Impagliazzo, G. Sartore
    On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications. [Citation Graph (0, 0)][DBLP]
    EDCC, 1996, pp:190-202 [Conf]
  5. Maurizio Damiani
    Nondeterministic finite-state machines and sequential don't cares. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:192-198 [Conf]
  6. Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani
    Scheduling with Environmental Constraints based on Automata Representations. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:495-501 [Conf]
  7. Valeria Bertacco, Maurizio Damiani
    Boolean Function Representation Using Parallel-Access Diagrams. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:112-117 [Conf]
  8. Valeria Bertacco, Maurizio Damiani
    The disjunctive decomposition of logic functions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:78-82 [Conf]
  9. Maurizio Damiani, Giovanni De Micheli
    Observability Don't Care Sets and Boolean Relations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:502-505 [Conf]
  10. Valeria Bertacco, Maurizio Damiani
    Boolean Function Representation Based on Disjoint-Support Decompositions. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:27-0 [Conf]
  11. Jérôme Fron, Jerry Chih-Yuan Yang, Maurizio Damiani, Giovanni De Micheli
    A Synthesis Framework Based on Trace and Automata Theory. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:291-294 [Conf]
  12. Vishwani D. Agrawal, Ronald D. Blanton, Maurizio Damiani
    Synthesis of Self-Testing Finite State Machines from High-Level Specifications. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:757-766 [Conf]
  13. Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò
    CMOS Design for Improved IC Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:934- [Conf]
  14. Piero Olivo, Maurizio Damiani, Bruno Riccò
    On the Design of Multiple-Input Shift-Registers for Signature Analysis Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:936- [Conf]
  15. Maurizio Damiani, Andrei Y. Selchenko
    Boolean Technology Mapping Based on Logic Decomposition. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:35-40 [Conf]
  16. Alessandro Bogliolo, Maurizio Damiani
    Synthesis of combinational circuits with special fault-handling capabilitie. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:454-459 [Conf]
  17. Alessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò
    Reliability evaluation of combinational logic circuits by symbolic simulation. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:235-243 [Conf]
  18. Maurizio Damiani, Piero Olivo, Bruno Riccò
    Analysis and Design of Linear Finite State Machines for Signature Analysis Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:9, pp:1034-1045 [Journal]
  19. Maurizio Damiani
    The state reduction of nondeterministic finite-state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1278-1291 [Journal]
  20. Maurizio Damiani, Giovanni De Micheli
    Don't care set specifications in combinational and synchronous logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:3, pp:365-388 [Journal]
  21. Maurizio Damiani, Piero Olivo, Michele Favalli, Silvia Ercolani, Bruno Riccò
    Aliasing in signature analysis testing with multiple input shift registers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1344-1353 [Journal]
  22. Maurizio Damiani, Piero Olivo, Michele Favalli, Bruno Riccò
    An analytical model for the aliasing probability in signature analysis testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1133-1144 [Journal]
  23. Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli
    Optimization of combinational logic circuits based on compatible gates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1316-1327 [Journal]
  24. Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò
    Testability measures in pseudorandom testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:794-800 [Journal]
  25. Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò
    Fault simulation of unconventional faults in CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:677-682 [Journal]
  26. Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani
    Scheduling and control generation with environmental constraints based on automata representations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:166-183 [Journal]
  27. Alessandro Bogliolo, Michele Favalli, Maurizio Damiani
    Enabling testability of fault-tolerant circuits by means of IDDQ-checkable voters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:415-419 [Journal]

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