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Publications of Author

1. Hamid R. Zarandi, Seyed Ghassem Miremadi, Shaahin Hessabi, Ali Reza Ejlali
   A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models. [Citation Graph (0, 0)][DBLP]
   ESA/VLSI, 2004, pp:582-588 [Conf]
   
2. Ali Reza Ejlali, Seyed Ghassem Miremadi
   Switch-level emulation. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:644-649 [Conf]
   
3. Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali
   Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models. [Citation Graph (0, 0)][DBLP]
   DFT, 2003, pp:485-492 [Conf]
   
4. Ali Reza Ejlali, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ghazanfar Asadi, Siavash Bayat Sarmadi
   A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation. [Citation Graph (0, 0)][DBLP]
   DSN, 2003, pp:479-0 [Conf]
   
5. Seyed Ghassem Miremadi, Ali Reza Ejlali
   Switch Level Fault Emulation. [Citation Graph (0, 0)][DBLP]
   FPL, 2003, pp:849-858 [Conf]
   
6. Siavash Bayat Sarmadi, Seyed Ghassem Miremadi, Ghazanfar Asadi, Ali Reza Ejlali
   Fast Prototyping with Co-operation of Simulation and Emulation. [Citation Graph (0, 0)][DBLP]
   FPL, 2002, pp:15-25 [Conf]
   
7. Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali
   Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems. [Citation Graph (0, 0)][DBLP]
   ISPDC, 2003, pp:281-0 [Conf]
   
8. Somayeh Timarchi, Seyed Ghassem Miremadi, Ali Reza Ejlali
   Evaluation of Some Exponential Random Number Generators Implemented by FPGA. [Citation Graph (0, 0)][DBLP]
   Parallel and Distributed Computing and Networks, 2005, pp:578-583 [Conf]
   
9. Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ali Reza Ejlali
   Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
   PRDC, 2004, pp:327-332 [Conf]