Conferences in DBLP
Thomas Schubert High level formal verification of next-generation microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Yves Mathys , André Chátelain Verification strategy for integration 3G baseband SoC. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus-Dieter Schubert Improvements in functional simulation addressing challenges in large, distributed industry projects. [Citation Graph (0, 0)][DBLP ] Conf ] Jan M. Rabaey , Dennis Sylvester , David Blaauw , Kerry Bernstein , Jerry Frenkil , Mark Horowitz , Wolfgang Nebel , Takayasu Sakurai , Andrew Yang Reshaping EDA for power. [Citation Graph (0, 0)][DBLP ] Conf ] Puneet Gupta , Andrew B. Kahng , Dennis Sylvester , Jie Yang A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Chen , Puneet Gupta , Andrew B. Kahng Performance-impact limited area fill synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Raia T. Hadsell , Patrick H. Madden Improved global routing through congestion estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Ashok Jagannathan , Glenn Reinman , Michail Romesis Microarchitecture evaluation with physical planning. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Alberto Macii , Enrico Macii , Elvira Omerbegovic , Fabrizio Pro , Massimo Poncino Energy-aware design techniques for differential power analysis protection. [Citation Graph (0, 0)][DBLP ] Conf ] Franco Fummi , Giovanni Perbellini , Paolo Gallo , Massimo Poncino , Stefano Martini , Fabio Ricciato A timing-accurate modeling and simulation environment for networked embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Robertas Damasevicius , Giedrius Majauskas , Vytautas Stuikys Application of design patterns for hardware design. [Citation Graph (0, 0)][DBLP ] Conf ] George Kornaros , Ioannis Papaefstathiou , Aristides Nikologiannis , Nicholaos Zervos A fully-programmable memory management system optimizing queue handling at multi-gigabit rates. [Citation Graph (0, 0)][DBLP ] Conf ] David Hwang , Bo-Cheng Lai , Patrick Schaumont , Kazuo Sakiyama , Yi Fan , Shenglin Yang , Alireza Hodjat , Ingrid Verbauwhede Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system. [Citation Graph (0, 0)][DBLP ] Conf ] Jennifer L. Wong , Seapahn Megerian , Miodrag Potkonjak Design techniques for sensor appliances: foundations and light compass case study. [Citation Graph (0, 0)][DBLP ] Conf ] Uri Barkai Seamless multi-radio integration challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Pieter W. Hooijmans RF front end application and technology trends. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Craninckx , Stéphane Donnay 4G terminals: how are we going to design them? [Citation Graph (0, 0)][DBLP ] Conf ] David E. Root , John Wood , Nick Tufillaro New techniques for non-linear behavioral modeling of microwave/RF ICs from simulation and nonlinear microwave measurements. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Dahlberg , Shishpal Rawat , Jen Bernier , Gina Gloski , Aurangzeb Khan , Kaushik Patel , Paul Ruddy , Naveed A. Sherwani , Ronnie Vasishta COT - customer owned trouble. [Citation Graph (0, 0)][DBLP ] Conf ] Haifeng Qian , Sani R. Nassif , Sachin S. Sapatnekar Random walks in a supply network. [Citation Graph (0, 0)][DBLP ] Conf ] Dionysios Kouroussis , Farid N. Najm A static pattern-independent technique for power grid voltage integrity verification. [Citation Graph (0, 0)][DBLP ] Conf ] Zhengyong Zhu , Bo Yao , Chung-Kuan Cheng Power network analysis using an adaptive algebraic multigrid approach. [Citation Graph (0, 0)][DBLP ] Conf ] Haihua Su , Emrah Acar , Sani R. Nassif Power grid reduction based on algebraic multigrid principles. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Wang , Malgorzata Marek-Sadowska On-chip power supply network optimization using multigrid-based technique. [Citation Graph (0, 0)][DBLP ] Conf ] Dexin Li , Qiang Xie , Pai H. Chou Scalable modeling and optimization of mode transitions based on decoupled power management architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Woo-Cheol Kwon , Taewhan Kim Optimal voltage allocation techniques for dynamically variable voltage processors. [Citation Graph (0, 0)][DBLP ] Conf ] Shaoxiong Hua , Gang Qu , Shuvra S. Bhattacharyya Energy reduction techniques for multimedia applications with tolerance to deadline misses. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Ramachandran , Margarida F. Jacome Xtream-Fit: an energy-delay efficient data memory subsystem for embedded media processing. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Mishchenko , Xinning Wang , Timothy Kam A new enhanced constructive decomposition and mapping algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Mishchenko , Tsutomu Sasao Large-scale SOP minimization using decomposition and functional properties. [Citation Graph (0, 0)][DBLP ] Conf ] Yunjian Jiang , Slobodan Matic , Robert K. Brayton Generalized cofactoring for logic function evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen A. Edwards Making cyclic circuits acyclic. [Citation Graph (0, 0)][DBLP ] Conf ] Marc D. Riedel , Jehoshua Bruck The synthesis of cyclic combinational circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Saibal Mukhopadhyay , Arijit Raychowdhury , Kaushik Roy Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Dongwoo Lee , Wesley Kwong , David Blaauw , Dennis Sylvester Analysis and minimization techniques for total leakage considering gate oxide leakage. [Citation Graph (0, 0)][DBLP ] Conf ] Changbo Long , Lei He Distributed sleep transistor network for power reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Yuh-Fang Tsai , David Duarte , Narayanan Vijaykrishnan , Mary Jane Irwin Implications of technology scaling on leakage reduction techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Dongwoo Lee , David Blaauw Static leakage reduction through simultaneous threshold voltage and state assignment. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Foon Chan , Deirdre Hanford , Jian Yue Pan , Narendra V. Shenoy , Mahesh Mehendale , A. Vasudevan , Shaojun Wei Emerging markets: design goes global. [Citation Graph (0, 0)][DBLP ] Conf ] Giancarlo Beraudo , John Lillis Timing optimization of FPGA placements by logic replication. [Citation Graph (0, 0)][DBLP ] Conf ] Chao-Yang Yeh , Malgorzata Marek-Sadowska Delay budgeting in sequential circuit with application on FPGA placement. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Xin Yuan Multilevel global placement with retiming. [Citation Graph (0, 0)][DBLP ] Conf ] Sung-Woo Hur , Tung Cao , Karthik Rajagopal , Yegna Parasuram , Amit Chowdhary , Vladimir Tiourin , Bill Halpin Force directed mongrel with physical net constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Zhanhai Qin , Chung-Kuan Cheng Realizable parasitic reduction using generalized Y-Delta transformation. [Citation Graph (0, 0)][DBLP ] Conf ] Chirayu S. Amin , Masud H. Chowdhury , Yehea I. Ismail Realizable RLCK circuit crunching. [Citation Graph (0, 0)][DBLP ] Conf ] Shizhong Mei , Chirayu S. Amin , Yehea I. Ismail Efficient model order reduction including skin effect. [Citation Graph (0, 0)][DBLP ] Conf ] Emad Gad , Michel S. Nakhla Model order reduction of nonuniform transmission lines using integrated congruence transform. [Citation Graph (0, 0)][DBLP ] Conf ] Radoslaw Szymanek , Krzysztof Kuchcinski Partial task assignment of task graphs under heterogeneous resource constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Greg Stitt , Roman L. Lysecky , Frank Vahid Dynamic hardware/software partitioning: a first approach. [Citation Graph (0, 0)][DBLP ] Conf ] Kubilay Atasu , Laura Pozzi , Paolo Ienne Automatic application-specific instruction-set extensions under microarchitectural constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Achim Nohl , Volker Greive , Gunnar Braun , Andreas Hoffmann , Rainer Leupers , Oliver Schliebusch , Heinrich Meyr Instruction encoding synthesis for architecture exploration using hierarchical processor models. [Citation Graph (0, 0)][DBLP ] Conf ] Gary H. Bernstein Quantum-dot cellular automata: computing by field polarization. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Wasshuber Recent advances and future prospects in single-electronics. [Citation Graph (0, 0)][DBLP ] Conf ] Islamshah Amlani , Ruth Zhang , John Tresek , Larry Nagahara , Raymond K. Tsui Manipulation and characterization of molecular scale components. [Citation Graph (0, 0)][DBLP ] Conf ] Rob A. Rutenbar , David L. Harame , Kurt Johnson , Paul Kempf , Teresa H. Y. Meng , Reza Rofougaran , James Spoto Mixed signals on mixed-signal: the right next technology. [Citation Graph (0, 0)][DBLP ] Conf ] Alon Gluska Coverage-oriented verification of banias. [Citation Graph (0, 0)][DBLP ] Conf ] Shai Fine , Avi Ziv Coverage directed test generation for functional verification using bayesian networks. [Citation Graph (0, 0)][DBLP ] Conf ] Nikhil Jayakumar , Mitra Purandare , Fabio Somenzi Dos and don'ts of CTL state coverage estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Yuan , Ken Albin , Adnan Aziz , Carl Pixley Constraint synthesis for environment modeling in functional verification. [Citation Graph (0, 0)][DBLP ] Conf ] Samar Abdi , Dongwan Shin , Daniel Gajski Automatic communication refinement for system level design. [Citation Graph (0, 0)][DBLP ] Conf ] Haris Lekatsas , Jörg Henkel , Srimat T. Chakradhar , Venkata Jakkula , Murugan Sankaradass CoCo: a hardware/software platform for rapid prototyping of code compression technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Trevor Meyerowitz , Claudio Pinello , Alberto L. Sangiovanni-Vincentelli A tool for describing and evaluating hierarchical real-time bus scheduling policies. [Citation Graph (0, 0)][DBLP ] Conf ] D. Michael Miller , Dmitri Maslov , Gerhard W. Dueck A transformation based algorithm for reversible logic synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen S. Bullock , Igor L. Markov An arbitrary twoqubit computation In 23 elementary gates or less. [Citation Graph (0, 0)][DBLP ] Conf ] Arash Saifhashemi , Hossein Pedram Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction. [Citation Graph (0, 0)][DBLP ] Conf ] Roman L. Lysecky , Frank Vahid On-chip logic minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Shekhar Borkar , Tanay Karnik , Siva Narendra , James Tschanz , Ali Keshavarzi , Vivek De Parameter variations and impact on circuits and microarchitecture. [Citation Graph (0, 0)][DBLP ] Conf ] Chandu Visweswariah Death, taxes and failing chips. [Citation Graph (0, 0)][DBLP ] Conf ] Aseem Agarwal , David Blaauw , Vladimir Zolotov , Sarma B. K. Vrudhula Computation and Refinement of Statistical Bounds on Circuit Delay. [Citation Graph (0, 0)][DBLP ] Conf ] Abbas El Gamal , Ivo Bolsens , Andy Broom , Christopher Hamlin , Philippe Magarshack , Zvi Or-Bach , Lawrence T. Pileggi Fast, cheap and under control: the next implementation fabric. [Citation Graph (0, 0)][DBLP ] Conf ] Serdar Tasiran , Yuan Yu , Brannon Batson Using a formal specification and a model checker to monitor and direct simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Chin Hsu , Bassam Tabbara , Yirng-An Chen , Fur-Shing Tsai Advanced techniques for RTL debugging. [Citation Graph (0, 0)][DBLP ] Conf ] Edmund M. Clarke , Daniel Kroening , Karen Yorav Behavioral consistency of C and verilog programs using bounded model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Renate Henftling , Andreas Zinn , Matthias Bauer , Martin Zambaldi , Wolfgang Ecker Re-use-centric architecture for a fully accelerated testbench environment. [Citation Graph (0, 0)][DBLP ] Conf ] Kanak Agarwal , Dennis Sylvester , David Blaauw An effective capacitance based driver output model for on-chip RLC interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Charles J. Alpert , Frank Liu , Chandramouli V. Kashyap , Anirudh Devgan Delay and slew metrics using the lognormal distribution. [Citation Graph (0, 0)][DBLP ] Conf ] John F. Croix , D. F. Wong Blade and razor: cell and interconnect delay analysis using current-based models. [Citation Graph (0, 0)][DBLP ] Conf ] Bhavana Thudi , David Blaauw Non-iterative switching window computation for delay-noise. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffry T. Russell , Margarida F. Jacome Architecture-level performance evaluation of component-based embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Andy D. Pimentel , Cagkan Erbas An IDF-based trace transformation method for communication refinement. [Citation Graph (0, 0)][DBLP ] Conf ] JoAnn M. Paul , Alex Bobrek , Jeffrey E. Nelson , Joshua J. Pieper , Donald E. Thomas Schedulers as model-based design elements in programmable heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Satya Kiran , M. N. Jayram , Pradeep Rao , S. K. Nandy A complexity effective communication model for behavioral modeling of signal processing applications. [Citation Graph (0, 0)][DBLP ] Conf ] Greg Spirakis Leading-edge and future design challenges - is the classical EDA ready? [Citation Graph (0, 0)][DBLP ] Conf ] Akira Matsuzawa How to make efficient communication, collaboration, and optimization from system to chip. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Magarshack , Pierre G. Paulin System-on-chip beyond the nanometer wall. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjit A. Seshia , Shuvendu K. Lahiri , Randal E. Bryant A hybrid SAT-based decision procedure for separation logic with uninterpreted functions. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Goel , Gagan Hasteer , Randal E. Bryant Symbolic representation with ordered function templates. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Lu , Li-C. Wang , Kwang-Ting Cheng , John Moondanos , Ziyad Hanna A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. [Citation Graph (0, 0)][DBLP ] Conf ] Kelvin Ng , Mukul R. Prasad , Rajarshi Mukherjee , Jawahar Jain Solving the latch mapping problem in an industrial setting. [Citation Graph (0, 0)][DBLP ] Conf ] Giovanni Agosta , Francesco Bruschi , Donatella Sciuto Static analysis of transaction-level models. [Citation Graph (0, 0)][DBLP ] Conf ] Marek Jersak , Rolf Ernst Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervals. [Citation Graph (0, 0)][DBLP ] Conf ] Xi Chen , Harry Hsieh , Felice Balarin , Yosinori Watanabe Automatic trace analysis for logic of constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Xianfeng Li , Tulika Mitra , Abhik Roychoudhury Accurate timing analysis by modeling caches, speculation and their interaction. [Citation Graph (0, 0)][DBLP ] Conf ] Peng Li , Lawrence T. Pileggi NORM: compact model order reduction of weakly nonlinear systems. [Citation Graph (0, 0)][DBLP ] Conf ] Xin Li , Peng Li , Yang Xu , Lawrence T. Pileggi Analog and RF circuit macromodels for system-level analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Ning Dong , Jaijeet S. Roychowdhury Piecewise polynomial nonlinear model reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Dmitry Vasilyev , Michal Rewienski , Jacob White A TBR-based trajectory piecewise-linear algorithm for generating accurate low-order models for nonlinear analog circuits and MEMS. [Citation Graph (0, 0)][DBLP ] Conf ] Claire Fang Fang , Rob A. Rutenbar , Markus Püschel , Tsuhan Chen Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Manish Amde , Ivan Blunno , Christos P. Sotiriou Automating the design of an asynchronous DLX microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Catherine G. Wong , Alain J. Martin High-level synthesis of asynchronous systems by data-driven decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Byoungro So , Pedro C. Diniz , Mary W. Hall Using estimates from behavioral synthesis tools in compiler-directed design space exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Robert M. Senger , Eric D. Marsman , Michael S. McCorquodale , Fadi H. Gebara , Keith L. Kraver , Matthew R. Guthaus , Richard B. Brown A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference. [Citation Graph (0, 0)][DBLP ] Conf ] Charlotte Y. Lau , Michael H. Perrott Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Payam Heydari Characterizing the effects of clock jitter due to substrate noise in discrete-time D/S modulators. [Citation Graph (0, 0)][DBLP ] Conf ] Vinita Vasudevan , M. Ramakrishna Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique. [Citation Graph (0, 0)][DBLP ] Conf ] Alicia Manthe , Zhao Li , C.-J. Richard Shi Symbolic analysis of analog circuits with hard nonlinearity. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Shekhar Borkar , John Cohn , Antun Domic , Patrick Groeneveld , Louis Scheffer , Jean-Pierre Schoellkopf Nanometer design: place your bets. [Citation Graph (0, 0)][DBLP ] Conf ] Li Chen , Srivaths Ravi , Anand Raghunathan , Sujit Dey A scalable software-based self-test methodology for programmable processors. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Li , Chaowen Yu , Sudhakar M. Reddy , Irith Pomeranz A scan BIST generation method using a markov source and partial bit-fixing. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmad A. Al-Yamani , Edward J. McCluskey Seed encoding with LFSRs and cellular automata. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Wohl , John A. Waicukauski , Sanjay Patel , Minesh B. Amin Efficient compression and application of deterministic patterns in a logic BIST architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Marcelo Negreiros , Luigi Carro , Altamiro Amadeu Susin Ultimate low cost analog BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Bo Hu , Yosinori Watanabe , Alex Kondratyev , Malgorzata Marek-Sadowska Gain-based technology mapping for discrete-size cell libraries. [Citation Graph (0, 0)][DBLP ] Conf ] Weiping Shi , Zhuo Li An O(nlogn) time algorithm for optimal buffer insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Maged Ghoneima , Yehea I. Ismail Optimum positioning of interleaved repeaters In bidirectional buses. [Citation Graph (0, 0)][DBLP ] Conf ] Jihong Ren , Mark R. Greenstreet Synthesizing optimal filters for crosstalk-cancellation for high-speed buses. [Citation Graph (0, 0)][DBLP ] Conf ] Pongstorn Maidee , Cristinel Ababei , Kia Bazargan Fast timing-driven partitioning-based placement for island style FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Seda Ogrenci Memik , Gokhan Memik , Roozbeh Jafari , Eren Kursun Global resource sharing for synthesis of control data flow graphs on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Heidi E. Ziegler , Mary W. Hall , Pedro C. Diniz Compiler-generated communication for pipelined FPGA applications. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Kaplan , Philip Brisk , Ryan Kastner Data communication estimation and reduction for reconfigurable systems. [Citation Graph (0, 0)][DBLP ] Conf ] Monica Donno , Alessandro Ivaldi , Luca Benini , Enrico Macii Clock-tree power optimization based on RTL clock-gating. [Citation Graph (0, 0)][DBLP ] Conf ] Rizwan Bashirullah , Wentai Liu , Ralph K. Cavin III Low-power design methodology for an on-chip bus with adaptive bandwidth capability. [Citation Graph (0, 0)][DBLP ] Conf ] Tali Moreshet , R. Iris Bahar Power-aware issue queue design for speculative instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Reinaldo A. Bergamaschi , Yunjian Jiang State-based power analysis for systems-on-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Carl Sechen , Barbara Chappel , Jim Hogan , Andrew Moore , Tadahiko Nakamura , Gregory A. Northrop , Anjaneya Thakar Libraries: lifejacket or straitjacket. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Reza Ejlali , Seyed Ghassem Miremadi Switch-level emulation. [Citation Graph (0, 0)][DBLP ] Conf ] Fernanda Lima , Luigi Carro , Ricardo Augusto da Luz Reis Designing fault tolerant systems into SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Joan Carletta , Robert J. Veillette , Frederick W. Krach , Zhengwei Fang Determining appropriate precisions for signals in fixed-point IIR filters. [Citation Graph (0, 0)][DBLP ] Conf ] Xijiang Lin , Rob Thompson Test generation for designs with multiple clocks. [Citation Graph (0, 0)][DBLP ] Conf ] Angela Krstic , Li-C. Wang , Kwang-Ting Cheng , Jing-Jia Liou , T. M. Mak Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Huang , Wu-Tung Cheng Using embedded infrastructure IP for SOC post-silicon verification. [Citation Graph (0, 0)][DBLP ] Conf ] Mehdi Baradaran Tahoori Using satisfiability in application-dependent testing of FPGA interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Frank O'Mahony , C. Patrick Yue , Mark Horowitz , S. Simon Wong Design of a 10GHz clock distribution network using coupled standing-wave oscillators. [Citation Graph (0, 0)][DBLP ] Conf ] John G. Maneatis , Jaeha Kim , Iain McClatchie , Jay Maxey , Manjusha Shankaradas Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL. [Citation Graph (0, 0)][DBLP ] Conf ] Michele Borgatti , L. Cali , Guido De Sandre , B. Forét , D. Iezzi , Francesco Lertora , G. Muzzi , Marco Pasotti , Marco Poles , Pier Luigi Rolandi A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory. [Citation Graph (0, 0)][DBLP ] Conf ] Yiu-Hing Chan , Prabhakar Kudva , Lisa B. Lacey , Gregory A. Northrop , Thomas E. Rosser Physical synthesis methodology for high performance microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Hisashige Ando , Yuuji Yoshida , Aiichiro Inoue , Itsumi Sugiyama , Takeo Asakawa , Kuniki Morita , Toshiyuki Muta , Tsuyoshi Motokurumada , Seishi Okada , Hideo Yamashita , Yoshihiko Satsukawa , Akihiko Konmoto , Ryouichi Yamashita , Hiroyuki Sugiyama A 1.3GHz fifth generation SPARC64 microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Stinson , Stefan Rusu A 1.5GHz third generation itanium® 2 processor. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh K. Gupta , Shishpal Rawat , Sandeep K. Shukla , Brian Bailey , Daniel K. Beece , Masahiro Fujita , Carl Pixley , John O'Leary , Fabio Somenzi Formal verification - prove it or pitch it. [Citation Graph (0, 0)][DBLP ] Conf ] Zhenhai Zhu , Ben Song , Jacob White Algorithms in FastImp: a fast and wideband impedance extraction program for complicated 3-D geometries. [Citation Graph (0, 0)][DBLP ] Conf ] Hao Yu , Lei He Vector potential equivalent circuit based on PEEC inversion. [Citation Graph (0, 0)][DBLP ] Conf ] David Goren , Michael Zelikson , Rachel Gordin , Israel A. Wagner , Anastasia Barger , Alon Amir , Betty Livshitz , Anatoly Sherman , Youri Tretiakov , Robert A. Groves , J. Park , Donald L. Jordan , Sue E. Strang , R. Singh , Carl E. Dickey , David L. Harame On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices. [Citation Graph (0, 0)][DBLP ] Conf ] Guoan Zhong , Cheng-Kok Koh , Venkataramanan Balakrishnan , Kaushik Roy An adaptive window-based susceptance extraction and its efficient implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Wenjing Rao , Ismet Bayraktaroglu , Alex Orailoglu Test application time and volume compression through seed overlapping. [Citation Graph (0, 0)][DBLP ] Conf ] Anuja Sehgal , Vikram Iyengar , Mark D. Krasniewski , Krishnendu Chakrabarty Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Xiang , Shan Gu , Jia-Guang Sun , Yu-Liang Wu A cost-effective scan architecture for scan testing with non-scan test power and test application cost. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On test data compression and n-detection test sets. [Citation Graph (0, 0)][DBLP ] Conf ] Wai Sum Mong , Jianwen Zhu A retargetable micro-architecture simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Mehrdad Reshadi , Prabhat Mishra , Nikil D. Dutt Instruction set compiled simulation: a technique for fast and flexible instruction set simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Qin , Sharad Malik Automated synthesis of efficient binary decoders for retargetable software toolkits. [Citation Graph (0, 0)][DBLP ] Conf ] David E. Lackey , Paul S. Zuchowski , Jürgen Koehl Designing mega-ASICs in nanogate technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Clive Bittlestone , Anthony M. Hill , Vipul Singhal , N. V. Arvind Architecting ASIC libraries and flows in nanometer era. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence T. Pileggi , Herman Schmit , Andrzej J. Strojwas , Padmini Gopalakrishnan , V. Kheterpal , Aneesh Koorapaty , Chetan Patel , V. Rovner , K. Y. Tong Exploring regular fabrics to optimize the performance-cost trade-off. [Citation Graph (0, 0)][DBLP ] Conf ] Ruchir Puri , Leon Stok , John M. Cohn , David S. Kung , David Z. Pan , Dennis Sylvester , Ashish Srivastava , Sarvesh H. Kulkarni Pushing ASIC performance in a power envelope. [Citation Graph (0, 0)][DBLP ] Conf ] Hongyu Chen , Chung-Kuan Cheng , Nan-Chi Chou , Andrew B. Kahng , John F. MacDonald , Peter Suaris , Bo Yao , Zhengyong Zhu An algebraic multigrid solver for analytical placement with layout based clustering. [Citation Graph (0, 0)][DBLP ] Conf ] Bo Hu , Malgorzata Marek-Sadowska Wire length prediction based clustering and its application in placement. [Citation Graph (0, 0)][DBLP ] Conf ] Yuchun Ma , Xianlong Hong , Sheqin Dong , Song Chen , Yici Cai , Chung-Kuan Cheng , Jun Gu Dynamic global buffer planning optimization based on detail block locating and congestion analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Hsun-Cheng Lee , Yao-Wen Chang , Jer-Ming Hsu , Hannah Honghua Yang Multilevel floorplanning/placement for large-scale modules using B*-trees. [Citation Graph (0, 0)][DBLP ] Conf ] Robert F. Damiano , James H. Kukula Checking satisfiability of a conjunction of BDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Aarti Gupta , Malay K. Ganai , Chao Wang , Zijiang Yang , Pranav Ashar Learning from BDDs in SAT-based bounded model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Donald Chai , Andreas Kuehlmann A fast pseudo-boolean constraint solver. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi A. Aloul , Igor L. Markov , Karem A. Sakallah Shatter: efficient symmetry-breaking for boolean satisfiability. [Citation Graph (0, 0)][DBLP ] Conf ] Hyeong-Ju Kang , In-Cheol Park SAT-based unbounded symbolic model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Gilles-Eric Descamps , Satish Bagalkotkar , Subramaniam Ganesan , Satish Iyengar , Alain Pirson Design of a 17-million gate network processor using a design factory. [Citation Graph (0, 0)][DBLP ] Conf ] Kaijian Shi , Graig Godwin Hybrid hierarchical timing closure methodology for a high performance and low power DSP. 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