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Conferences in DBLP

Design Automation Conference (DAC) (dac)
2003 (conf/dac/2003)

  1. Thomas Schubert
    High level formal verification of next-generation microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:1-6 [Conf]
  2. Yves Mathys, André Chátelain
    Verification strategy for integration 3G baseband SoC. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:7-10 [Conf]
  3. Klaus-Dieter Schubert
    Improvements in functional simulation addressing challenges in large, distributed industry projects. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:11-14 [Conf]
  4. Jan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang
    Reshaping EDA for power. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:15- [Conf]
  5. Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
    A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:16-21 [Conf]
  6. Yu Chen, Puneet Gupta, Andrew B. Kahng
    Performance-impact limited area fill synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:22-27 [Conf]
  7. Raia T. Hadsell, Patrick H. Madden
    Improved global routing through congestion estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:28-31 [Conf]
  8. Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis
    Microarchitecture evaluation with physical planning. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:32-35 [Conf]
  9. Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Fabrizio Pro, Massimo Poncino
    Energy-aware design techniques for differential power analysis protection. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:36-41 [Conf]
  10. Franco Fummi, Giovanni Perbellini, Paolo Gallo, Massimo Poncino, Stefano Martini, Fabio Ricciato
    A timing-accurate modeling and simulation environment for networked embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:42-47 [Conf]
  11. Robertas Damasevicius, Giedrius Majauskas, Vytautas Stuikys
    Application of design patterns for hardware design. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:48-53 [Conf]
  12. George Kornaros, Ioannis Papaefstathiou, Aristides Nikologiannis, Nicholaos Zervos
    A fully-programmable memory management system optimizing queue handling at multi-gigabit rates. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:54-59 [Conf]
  13. David Hwang, Bo-Cheng Lai, Patrick Schaumont, Kazuo Sakiyama, Yi Fan, Shenglin Yang, Alireza Hodjat, Ingrid Verbauwhede
    Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:60-65 [Conf]
  14. Jennifer L. Wong, Seapahn Megerian, Miodrag Potkonjak
    Design techniques for sensor appliances: foundations and light compass case study. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:66-71 [Conf]
  15. Uri Barkai
    Seamless multi-radio integration challenges. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:72- [Conf]
  16. Pieter W. Hooijmans
    RF front end application and technology trends. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:73-78 [Conf]
  17. Jan Craninckx, Stéphane Donnay
    4G terminals: how are we going to design them? [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:79-84 [Conf]
  18. David E. Root, John Wood, Nick Tufillaro
    New techniques for non-linear behavioral modeling of microwave/RF ICs from simulation and nonlinear microwave measurements. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:85-90 [Conf]
  19. Robert Dahlberg, Shishpal Rawat, Jen Bernier, Gina Gloski, Aurangzeb Khan, Kaushik Patel, Paul Ruddy, Naveed A. Sherwani, Ronnie Vasishta
    COT - customer owned trouble. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:91-92 [Conf]
  20. Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
    Random walks in a supply network. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:93-98 [Conf]
  21. Dionysios Kouroussis, Farid N. Najm
    A static pattern-independent technique for power grid voltage integrity verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:99-104 [Conf]
  22. Zhengyong Zhu, Bo Yao, Chung-Kuan Cheng
    Power network analysis using an adaptive algebraic multigrid approach. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:105-108 [Conf]
  23. Haihua Su, Emrah Acar, Sani R. Nassif
    Power grid reduction based on algebraic multigrid principles. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:109-112 [Conf]
  24. Kai Wang, Malgorzata Marek-Sadowska
    On-chip power supply network optimization using multigrid-based technique. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:113-118 [Conf]
  25. Dexin Li, Qiang Xie, Pai H. Chou
    Scalable modeling and optimization of mode transitions based on decoupled power management architecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:119-124 [Conf]
  26. Woo-Cheol Kwon, Taewhan Kim
    Optimal voltage allocation techniques for dynamically variable voltage processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:125-130 [Conf]
  27. Shaoxiong Hua, Gang Qu, Shuvra S. Bhattacharyya
    Energy reduction techniques for multimedia applications with tolerance to deadline misses. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:131-136 [Conf]
  28. Anand Ramachandran, Margarida F. Jacome
    Xtream-Fit: an energy-delay efficient data memory subsystem for embedded media processing. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:137-142 [Conf]
  29. Alan Mishchenko, Xinning Wang, Timothy Kam
    A new enhanced constructive decomposition and mapping algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:143-148 [Conf]
  30. Alan Mishchenko, Tsutomu Sasao
    Large-scale SOP minimization using decomposition and functional properties. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:149-154 [Conf]
  31. Yunjian Jiang, Slobodan Matic, Robert K. Brayton
    Generalized cofactoring for logic function evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:155-158 [Conf]
  32. Stephen A. Edwards
    Making cyclic circuits acyclic. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:159-162 [Conf]
  33. Marc D. Riedel, Jehoshua Bruck
    The synthesis of cyclic combinational circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:163-168 [Conf]
  34. Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy
    Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:169-174 [Conf]
  35. Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester
    Analysis and minimization techniques for total leakage considering gate oxide leakage. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:175-180 [Conf]
  36. Changbo Long, Lei He
    Distributed sleep transistor network for power reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:181-186 [Conf]
  37. Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
    Implications of technology scaling on leakage reduction techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:187-190 [Conf]
  38. Dongwoo Lee, David Blaauw
    Static leakage reduction through simultaneous threshold voltage and state assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:191-194 [Conf]
  39. Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei
    Emerging markets: design goes global. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:195- [Conf]
  40. Giancarlo Beraudo, John Lillis
    Timing optimization of FPGA placements by logic replication. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:196-201 [Conf]
  41. Chao-Yang Yeh, Malgorzata Marek-Sadowska
    Delay budgeting in sequential circuit with application on FPGA placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:202-207 [Conf]
  42. Jason Cong, Xin Yuan
    Multilevel global placement with retiming. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:208-213 [Conf]
  43. Sung-Woo Hur, Tung Cao, Karthik Rajagopal, Yegna Parasuram, Amit Chowdhary, Vladimir Tiourin, Bill Halpin
    Force directed mongrel with physical net constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:214-219 [Conf]
  44. Zhanhai Qin, Chung-Kuan Cheng
    Realizable parasitic reduction using generalized Y-Delta transformation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:220-225 [Conf]
  45. Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail
    Realizable RLCK circuit crunching. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:226-231 [Conf]
  46. Shizhong Mei, Chirayu S. Amin, Yehea I. Ismail
    Efficient model order reduction including skin effect. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:232-237 [Conf]
  47. Emad Gad, Michel S. Nakhla
    Model order reduction of nonuniform transmission lines using integrated congruence transform. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:238-243 [Conf]
  48. Radoslaw Szymanek, Krzysztof Kuchcinski
    Partial task assignment of task graphs under heterogeneous resource constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:244-249 [Conf]
  49. Greg Stitt, Roman L. Lysecky, Frank Vahid
    Dynamic hardware/software partitioning: a first approach. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:250-255 [Conf]
  50. Kubilay Atasu, Laura Pozzi, Paolo Ienne
    Automatic application-specific instruction-set extensions under microarchitectural constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:256-261 [Conf]
  51. Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr
    Instruction encoding synthesis for architecture exploration using hierarchical processor models. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:262-267 [Conf]
  52. Gary H. Bernstein
    Quantum-dot cellular automata: computing by field polarization. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:268-273 [Conf]
  53. Christoph Wasshuber
    Recent advances and future prospects in single-electronics. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:274-275 [Conf]
  54. Islamshah Amlani, Ruth Zhang, John Tresek, Larry Nagahara, Raymond K. Tsui
    Manipulation and characterization of molecular scale components. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:276-277 [Conf]
  55. Rob A. Rutenbar, David L. Harame, Kurt Johnson, Paul Kempf, Teresa H. Y. Meng, Reza Rofougaran, James Spoto
    Mixed signals on mixed-signal: the right next technology. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:278-279 [Conf]
  56. Alon Gluska
    Coverage-oriented verification of banias. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:280-285 [Conf]
  57. Shai Fine, Avi Ziv
    Coverage directed test generation for functional verification using bayesian networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:286-291 [Conf]
  58. Nikhil Jayakumar, Mitra Purandare, Fabio Somenzi
    Dos and don'ts of CTL state coverage estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:292-295 [Conf]
  59. Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley
    Constraint synthesis for environment modeling in functional verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:296-299 [Conf]
  60. Samar Abdi, Dongwan Shin, Daniel Gajski
    Automatic communication refinement for system level design. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:300-305 [Conf]
  61. Haris Lekatsas, Jörg Henkel, Srimat T. Chakradhar, Venkata Jakkula, Murugan Sankaradass
    CoCo: a hardware/software platform for rapid prototyping of code compression technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:306-311 [Conf]
  62. Trevor Meyerowitz, Claudio Pinello, Alberto L. Sangiovanni-Vincentelli
    A tool for describing and evaluating hierarchical real-time bus scheduling policies. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:312-317 [Conf]
  63. D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck
    A transformation based algorithm for reversible logic synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:318-323 [Conf]
  64. Stephen S. Bullock, Igor L. Markov
    An arbitrary twoqubit computation In 23 elementary gates or less. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:324-329 [Conf]
  65. Arash Saifhashemi, Hossein Pedram
    Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:330-333 [Conf]
  66. Roman L. Lysecky, Frank Vahid
    On-chip logic minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:334-337 [Conf]
  67. Shekhar Borkar, Tanay Karnik, Siva Narendra, James Tschanz, Ali Keshavarzi, Vivek De
    Parameter variations and impact on circuits and microarchitecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:338-342 [Conf]
  68. Chandu Visweswariah
    Death, taxes and failing chips. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:343-347 [Conf]
  69. Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
    Computation and Refinement of Statistical Bounds on Circuit Delay. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:348-353 [Conf]
  70. Abbas El Gamal, Ivo Bolsens, Andy Broom, Christopher Hamlin, Philippe Magarshack, Zvi Or-Bach, Lawrence T. Pileggi
    Fast, cheap and under control: the next implementation fabric. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:354-355 [Conf]
  71. Serdar Tasiran, Yuan Yu, Brannon Batson
    Using a formal specification and a model checker to monitor and direct simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:356-361 [Conf]
  72. Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai
    Advanced techniques for RTL debugging. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:362-367 [Conf]
  73. Edmund M. Clarke, Daniel Kroening, Karen Yorav
    Behavioral consistency of C and verilog programs using bounded model checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:368-371 [Conf]
  74. Renate Henftling, Andreas Zinn, Matthias Bauer, Martin Zambaldi, Wolfgang Ecker
    Re-use-centric architecture for a fully accelerated testbench environment. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:372-375 [Conf]
  75. Kanak Agarwal, Dennis Sylvester, David Blaauw
    An effective capacitance based driver output model for on-chip RLC interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:376-381 [Conf]
  76. Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
    Delay and slew metrics using the lognormal distribution. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:382-385 [Conf]
  77. John F. Croix, D. F. Wong
    Blade and razor: cell and interconnect delay analysis using current-based models. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:386-389 [Conf]
  78. Bhavana Thudi, David Blaauw
    Non-iterative switching window computation for delay-noise. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:390-395 [Conf]
  79. Jeffry T. Russell, Margarida F. Jacome
    Architecture-level performance evaluation of component-based embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:396-401 [Conf]
  80. Andy D. Pimentel, Cagkan Erbas
    An IDF-based trace transformation method for communication refinement. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:402-407 [Conf]
  81. JoAnn M. Paul, Alex Bobrek, Jeffrey E. Nelson, Joshua J. Pieper, Donald E. Thomas
    Schedulers as model-based design elements in programmable heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:408-411 [Conf]
  82. Satya Kiran, M. N. Jayram, Pradeep Rao, S. K. Nandy
    A complexity effective communication model for behavioral modeling of signal processing applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:412-415 [Conf]
  83. Greg Spirakis
    Leading-edge and future design challenges - is the classical EDA ready? [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:416- [Conf]
  84. Akira Matsuzawa
    How to make efficient communication, collaboration, and optimization from system to chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:417-418 [Conf]
  85. Philippe Magarshack, Pierre G. Paulin
    System-on-chip beyond the nanometer wall. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:419-424 [Conf]
  86. Sanjit A. Seshia, Shuvendu K. Lahiri, Randal E. Bryant
    A hybrid SAT-based decision procedure for separation logic with uninterpreted functions. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:425-430 [Conf]
  87. Amit Goel, Gagan Hasteer, Randal E. Bryant
    Symbolic representation with ordered function templates. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:431-435 [Conf]
  88. Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
    A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:436-441 [Conf]
  89. Kelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain
    Solving the latch mapping problem in an industrial setting. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:442-447 [Conf]
  90. Giovanni Agosta, Francesco Bruschi, Donatella Sciuto
    Static analysis of transaction-level models. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:448-453 [Conf]
  91. Marek Jersak, Rolf Ernst
    Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervals. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:454-459 [Conf]
  92. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
    Automatic trace analysis for logic of constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:460-465 [Conf]
  93. Xianfeng Li, Tulika Mitra, Abhik Roychoudhury
    Accurate timing analysis by modeling caches, speculation and their interaction. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:466-471 [Conf]
  94. Peng Li, Lawrence T. Pileggi
    NORM: compact model order reduction of weakly nonlinear systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:472-477 [Conf]
  95. Xin Li, Peng Li, Yang Xu, Lawrence T. Pileggi
    Analog and RF circuit macromodels for system-level analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:478-483 [Conf]
  96. Ning Dong, Jaijeet S. Roychowdhury
    Piecewise polynomial nonlinear model reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:484-489 [Conf]
  97. Dmitry Vasilyev, Michal Rewienski, Jacob White
    A TBR-based trajectory piecewise-linear algorithm for generating accurate low-order models for nonlinear analog circuits and MEMS. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:490-495 [Conf]
  98. Claire Fang Fang, Rob A. Rutenbar, Markus Püschel, Tsuhan Chen
    Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:496-501 [Conf]
  99. Manish Amde, Ivan Blunno, Christos P. Sotiriou
    Automating the design of an asynchronous DLX microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:502-507 [Conf]
  100. Catherine G. Wong, Alain J. Martin
    High-level synthesis of asynchronous systems by data-driven decomposition. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:508-513 [Conf]
  101. Byoungro So, Pedro C. Diniz, Mary W. Hall
    Using estimates from behavioral synthesis tools in compiler-directed design space exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:514-519 [Conf]
  102. Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Matthew R. Guthaus, Richard B. Brown
    A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:520-525 [Conf]
  103. Charlotte Y. Lau, Michael H. Perrott
    Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:526-531 [Conf]
  104. Payam Heydari
    Characterizing the effects of clock jitter due to substrate noise in discrete-time D/S modulators. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:532-537 [Conf]
  105. Vinita Vasudevan, M. Ramakrishna
    Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:538-541 [Conf]
  106. Alicia Manthe, Zhao Li, C.-J. Richard Shi
    Symbolic analysis of analog circuits with hard nonlinearity. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:542-545 [Conf]
  107. Andrew B. Kahng, Shekhar Borkar, John Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf
    Nanometer design: place your bets. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:546-547 [Conf]
  108. Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey
    A scalable software-based self-test methodology for programmable processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:548-553 [Conf]
  109. Wei Li, Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz
    A scan BIST generation method using a markov source and partial bit-fixing. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:554-559 [Conf]
  110. Ahmad A. Al-Yamani, Edward J. McCluskey
    Seed encoding with LFSRs and cellular automata. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:560-565 [Conf]
  111. Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin
    Efficient compression and application of deterministic patterns in a logic BIST architecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:566-569 [Conf]
  112. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Ultimate low cost analog BIST. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:570-573 [Conf]
  113. Bo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska
    Gain-based technology mapping for discrete-size cell libraries. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:574-579 [Conf]
  114. Weiping Shi, Zhuo Li
    An O(nlogn) time algorithm for optimal buffer insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:580-585 [Conf]
  115. Maged Ghoneima, Yehea I. Ismail
    Optimum positioning of interleaved repeaters In bidirectional buses. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:586-591 [Conf]
  116. Jihong Ren, Mark R. Greenstreet
    Synthesizing optimal filters for crosstalk-cancellation for high-speed buses. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:592-597 [Conf]
  117. Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
    Fast timing-driven partitioning-based placement for island style FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:598-603 [Conf]
  118. Seda Ogrenci Memik, Gokhan Memik, Roozbeh Jafari, Eren Kursun
    Global resource sharing for synthesis of control data flow graphs on FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:604-609 [Conf]
  119. Heidi E. Ziegler, Mary W. Hall, Pedro C. Diniz
    Compiler-generated communication for pipelined FPGA applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:610-615 [Conf]
  120. Adam Kaplan, Philip Brisk, Ryan Kastner
    Data communication estimation and reduction for reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:616-621 [Conf]
  121. Monica Donno, Alessandro Ivaldi, Luca Benini, Enrico Macii
    Clock-tree power optimization based on RTL clock-gating. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:622-627 [Conf]
  122. Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
    Low-power design methodology for an on-chip bus with adaptive bandwidth capability. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:628-633 [Conf]
  123. Tali Moreshet, R. Iris Bahar
    Power-aware issue queue design for speculative instructions. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:634-637 [Conf]
  124. Reinaldo A. Bergamaschi, Yunjian Jiang
    State-based power analysis for systems-on-chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:638-641 [Conf]
  125. Carl Sechen, Barbara Chappel, Jim Hogan, Andrew Moore, Tadahiko Nakamura, Gregory A. Northrop, Anjaneya Thakar
    Libraries: lifejacket or straitjacket. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:642-643 [Conf]
  126. Ali Reza Ejlali, Seyed Ghassem Miremadi
    Switch-level emulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:644-649 [Conf]
  127. Fernanda Lima, Luigi Carro, Ricardo Augusto da Luz Reis
    Designing fault tolerant systems into SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:650-655 [Conf]
  128. Joan Carletta, Robert J. Veillette, Frederick W. Krach, Zhengwei Fang
    Determining appropriate precisions for signals in fixed-point IIR filters. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:656-661 [Conf]
  129. Xijiang Lin, Rob Thompson
    Test generation for designs with multiple clocks. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:662-667 [Conf]
  130. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak
    Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:668-673 [Conf]
  131. Yu Huang, Wu-Tung Cheng
    Using embedded infrastructure IP for SOC post-silicon verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:674-677 [Conf]
  132. Mehdi Baradaran Tahoori
    Using satisfiability in application-dependent testing of FPGA interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:678-681 [Conf]
  133. Frank O'Mahony, C. Patrick Yue, Mark Horowitz, S. Simon Wong
    Design of a 10GHz clock distribution network using coupled standing-wave oscillators. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:682-687 [Conf]
  134. John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas
    Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:688-690 [Conf]
  135. Michele Borgatti, L. Cali, Guido De Sandre, B. Forét, D. Iezzi, Francesco Lertora, G. Muzzi, Marco Pasotti, Marco Poles, Pier Luigi Rolandi
    A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:691-695 [Conf]
  136. Yiu-Hing Chan, Prabhakar Kudva, Lisa B. Lacey, Gregory A. Northrop, Thomas E. Rosser
    Physical synthesis methodology for high performance microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:696-701 [Conf]
  137. Hisashige Ando, Yuuji Yoshida, Aiichiro Inoue, Itsumi Sugiyama, Takeo Asakawa, Kuniki Morita, Toshiyuki Muta, Tsuyoshi Motokurumada, Seishi Okada, Hideo Yamashita, Yoshihiko Satsukawa, Akihiko Konmoto, Ryouichi Yamashita, Hiroyuki Sugiyama
    A 1.3GHz fifth generation SPARC64 microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:702-705 [Conf]
  138. Jason Stinson, Stefan Rusu
    A 1.5GHz third generation itanium® 2 processor. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:706-709 [Conf]
  139. Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi
    Formal verification - prove it or pitch it. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:710-711 [Conf]
  140. Zhenhai Zhu, Ben Song, Jacob White
    Algorithms in FastImp: a fast and wideband impedance extraction program for complicated 3-D geometries. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:712-717 [Conf]
  141. Hao Yu, Lei He
    Vector potential equivalent circuit based on PEEC inversion. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:718-723 [Conf]
  142. David Goren, Michael Zelikson, Rachel Gordin, Israel A. Wagner, Anastasia Barger, Alon Amir, Betty Livshitz, Anatoly Sherman, Youri Tretiakov, Robert A. Groves, J. Park, Donald L. Jordan, Sue E. Strang, R. Singh, Carl E. Dickey, David L. Harame
    On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:724-727 [Conf]
  143. Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy
    An adaptive window-based susceptance extraction and its efficient implementation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:728-731 [Conf]
  144. Wenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu
    Test application time and volume compression through seed overlapping. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:732-737 [Conf]
  145. Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty
    Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:738-743 [Conf]
  146. Dong Xiang, Shan Gu, Jia-Guang Sun, Yu-Liang Wu
    A cost-effective scan architecture for scan testing with non-scan test power and test application cost. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:744-747 [Conf]
  147. Irith Pomeranz, Sudhakar M. Reddy
    On test data compression and n-detection test sets. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:748-751 [Conf]
  148. Wai Sum Mong, Jianwen Zhu
    A retargetable micro-architecture simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:752-757 [Conf]
  149. Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt
    Instruction set compiled simulation: a technique for fast and flexible instruction set simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:758-763 [Conf]
  150. Wei Qin, Sharad Malik
    Automated synthesis of efficient binary decoders for retargetable software toolkits. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:764-769 [Conf]
  151. David E. Lackey, Paul S. Zuchowski, Jürgen Koehl
    Designing mega-ASICs in nanogate technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:770-775 [Conf]
  152. Clive Bittlestone, Anthony M. Hill, Vipul Singhal, N. V. Arvind
    Architecting ASIC libraries and flows in nanometer era. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:776-781 [Conf]
  153. Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, V. Rovner, K. Y. Tong
    Exploring regular fabrics to optimize the performance-cost trade-off. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:782-787 [Conf]
  154. Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni
    Pushing ASIC performance in a power envelope. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:788-793 [Conf]
  155. Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu
    An algebraic multigrid solver for analytical placement with layout based clustering. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:794-799 [Conf]
  156. Bo Hu, Malgorzata Marek-Sadowska
    Wire length prediction based clustering and its application in placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:800-805 [Conf]
  157. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Dynamic global buffer planning optimization based on detail block locating and congestion analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:806-811 [Conf]
  158. Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang
    Multilevel floorplanning/placement for large-scale modules using B*-trees. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:812-817 [Conf]
  159. Robert F. Damiano, James H. Kukula
    Checking satisfiability of a conjunction of BDDs. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:818-823 [Conf]
  160. Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar
    Learning from BDDs in SAT-based bounded model checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:824-829 [Conf]
  161. Donald Chai, Andreas Kuehlmann
    A fast pseudo-boolean constraint solver. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:830-835 [Conf]
  162. Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    Shatter: efficient symmetry-breaking for boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:836-839 [Conf]
  163. Hyeong-Ju Kang, In-Cheol Park
    SAT-based unbounded symbolic model checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:840-843 [Conf]
  164. Gilles-Eric Descamps, Satish Bagalkotkar, Subramaniam Ganesan, Satish Iyengar, Alain Pirson
    Design of a 17-million gate network processor using a design factory. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:844-849 [Conf]
  165. Kaijian Shi, Graig Godwin
    Hybrid hierarchical timing closure methodology for a high performance and low power DSP. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:850-855 [Conf]
  166. Imad A. Ferzli, Farid N. Najm
    Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:856-859 [Conf]
  167. Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
    Temporofunctional crosstalk noise analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:860-863 [Conf]
  168. Ken Tseng, Vinod Kariat
    Static noise analysis with noise windows. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:864-868 [Conf]
  169. Prabhat Jain, G. Edward Suh, Srinivas Devadas
    Embedded intelligent SRAM. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:869-874 [Conf]
  170. Tony Givargis
    Improved indexing for cache miss reduction in embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:875-880 [Conf]
  171. Yoonseo Choi, Taewhan Kim
    Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:881-886 [Conf]
  172. Wei Zhang 0002, Guangyu Chen, Mahmut T. Kandemir, Mustafa Karaköy
    Interprocedural optimizations for improving data cache performance of array-intensive embedded applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:887-892 [Conf]
  173. John P. Hayes
    Tutorial: basic concepts in quantum circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:893- [Conf]
  174. Ben Travaglione
    Designing and implementing small quantum circuits and algorithms. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:894-899 [Conf]
  175. Vijay Raghunathan, Mani B. Srivastava, Rajesh K. Gupta
    A survey of techniques for energy efficient on-chip communication. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:900-905 [Conf]
  176. Peng Rong, Massoud Pedram
    Extending the lifetime of a network of battery-powered mobile devices by remote processing: a markovian decision-based approach. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:906-911 [Conf]
  177. Kihwan Choi, Kwanho Kim, Massoud Pedram
    Energy-aware MPEG-4 FGS streaming. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:912-915 [Conf]
  178. M. Josie Ammer, Michael Sheets, Tufan C. Karalar, Mika Kuulusa, Jan M. Rabaey
    A low-energy chip-set for wireless intercom. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:916-919 [Conf]
  179. Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
    Optimal integer delay budgeting on directed acyclic graphs. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:920-925 [Conf]
  180. David A. Penry, David I. August
    Optimizations for a simulator construction system supporting reusable components. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:926-931 [Conf]
  181. Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
    Statistical timing for parametric yield prediction of digital integrated circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:932-937 [Conf]
  182. Rajesh Kumar
    Interconnect and noise immunity design for the Pentium 4 processor. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:938-943 [Conf]
  183. Yajun Ran, Malgorzata Marek-Sadowska
    Crosstalk noise in FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:944-949 [Conf]
  184. Kanak Agarwal, Dennis Sylvester, David Blaauw
    Simple metrics for slew rate of RC circuits based on two circuit moments. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:950-953 [Conf]
  185. Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
    Post-route gate sizing for crosstalk noise reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:954-957 [Conf]
  186. Guido Stehr, Helmut E. Graeb, Kurt Antreich
    Performance trade-off analysis of analog circuits by normal-boundary intersection. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:958-963 [Conf]
  187. Fernando De Bernardinis, M. I. Jordan, Alberto L. Sangiovanni-Vincentelli
    Support vector machines for analog circuit performance representation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:964-969 [Conf]
  188. Maria del Mar Hershenson
    Efficient description of the design space of analog circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:970-973 [Conf]
  189. Martin Vogels, Georges G. E. Gielen
    Architectural selection of A/D converters. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:974-977 [Conf]
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