The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Pablo Viana: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid
    Configurable cache subsetting for fast cache tuning. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:695-700 [Conf]
  2. Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo
    Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:734-735 [Conf]
  3. Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo
    Exploring Memory Hierarchy with ArchC. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2003, pp:2-9 [Conf]
  4. Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros
    A one-shot configurable-cache tuner for improved energy and performance. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:755-760 [Conf]
  5. Andre Silva, Guilherme Esmeraldo, Edna Barros, Pablo Viana
    Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:3-9 [Conf]

  6. A table-based method for single-pass cache optimization. [Citation Graph (, )][DBLP]


  7. Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption. [Citation Graph (, )][DBLP]


Search in 0.002secs, Finished in 0.003secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002