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Walid A. Najjar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Walid A. Najjar, Jean-Luc Gaudiot
    Network Disconnection in Distributed Systems. [Citation Graph (1, 0)][DBLP]
    ICDCS, 1988, pp:554-561 [Conf]
  2. Jeffrey Hammes, Robert Rinker, A. P. Wim Böhm, Walid A. Najjar, Bruce A. Draper, J. Ross Beveridge
    Cameron: High level Language Compilation for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:236-244 [Conf]
  3. Dianne Miller, Walid A. Najjar
    Empirical Evaluation of Deterministic and Adaptive Routing with Constant-Area Routers. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1997, pp:64-0 [Conf]
  4. Robert Rinker, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper
    Compiling Image Processing Applications to Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:56-65 [Conf]
  5. Bruce A. Draper, Walid A. Najjar, A. P. Wim Böhm, Jeffrey Hammes, Robert Rinker, Charlie Ross, Monica Chawathe, José Bins
    Compiling and Optimizing Image Processing Algorithms for FPGAs. [Citation Graph (0, 0)][DBLP]
    CAMP, 2000, pp:222-231 [Conf]
  6. Dianne R. Kumar, Walid A. Najjar
    Combining Adaptive and Deterministic Routing: Evaluation of a Hybrid Router. [Citation Graph (0, 0)][DBLP]
    CANPC, 1999, pp:150-164 [Conf]
  7. Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar, Laxmi N. Bhuyan
    Power efficient encoding techniques for off-chip data buses. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:267-275 [Conf]
  8. Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm
    A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture. [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:116-125 [Conf]
  9. Susan Cotterell, Frank Vahid, Walid A. Najjar, Harry Hsieh
    First results with eBlocks: embedded systems building blocks. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:168-175 [Conf]
  10. Jean-Luc Gaudiot, Thomas DeBoni, John Feo, A. P. Wim Böhm, Walid A. Najjar, Patrick Miller
    The Sisal Project: Real World Functional Programming. [Citation Graph (0, 0)][DBLP]
    Compiler Optimizations for Scalable Parallel Systems Languages, 2001, pp:45-72 [Conf]
  11. Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers
    Optimized Generation of Data-Path from C Codes for FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:112-117 [Conf]
  12. Walid A. Najjar
    From Here to Main-stream: The Present and Future of Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:17- [Conf]
  13. Demetrios Zeinalipour-Yazti, Song Lin, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar
    MicroHash: An Efficient Index Structure for Flash-Based Sensor Devices. [Citation Graph (0, 0)][DBLP]
    FAST, 2005, pp:- [Conf]
  14. A. P. Wim Böhm, J. Ross Beveridge, Bruce A. Draper, Charlie Ross, Monica Chawathe, Walid A. Najjar
    Compiling ATR Probing Codes for Execution on FPGA Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:301-302 [Conf]
  15. Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi
    Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:239-0 [Conf]
  16. Lucas Roh, Walid A. Najjar, A. P. Wim Böhm
    Generation and Quantitative Evaluation of Dataflow Clusters. [Citation Graph (0, 0)][DBLP]
    FPCA, 1993, pp:159-168 [Conf]
  17. Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers
    A quantitative analysis of the speedup factors of FPGAs over processors. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:162-170 [Conf]
  18. Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid
    Techniques for synthesizing binaries to an advanced register/memory structure. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:118-124 [Conf]
  19. Dinesh C. Suresh, Jun Yang, Chuanjun Zhang, Banit Agrawal, Walid A. Najjar
    FV-MSB: A Scheme for Reducing Transition Activity on Data Buses. [Citation Graph (0, 0)][DBLP]
    HiPC, 2003, pp:44-54 [Conf]
  20. Greg Stitt, Frank Vahid, Walid A. Najjar
    A code refinement methodology for performance-improved synthesis from C. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:716-723 [Conf]
  21. Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang
    VALVE: Variable Length Value Encoder for Off-Chip Data Buses.. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:631-633 [Conf]
  22. Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar
    Data Acquisition in Sensor Networks with Large Memories. [Citation Graph (0, 0)][DBLP]
    ICDE Workshops, 2005, pp:1188- [Conf]
  23. Walid A. Najjar, Jean-Luc Gaudiot
    Multi-Level Execution In Data-Flow Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:32-39 [Conf]
  24. Walid A. Najjar
    "How Long is Your Belt?" Towards a Single Device for Multiple Functions. [Citation Graph (0, 0)][DBLP]
    ICPS, 2004, pp:19-19 [Conf]
  25. William Marcus Miller, Walid A. Najjar, A. P. Wim Böhm
    A model for dataflow based vector execution. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1994, pp:11-22 [Conf]
  26. Bruce A. Draper, A. P. Wim Böhm, Jeffrey Hammes, Walid A. Najjar, J. Ross Beveridge, Charlie Ross, Monica Chawathe, Mitesh Desai, José Bins
    Compiling SA-C Programs to FPGAs: Performance Results. [Citation Graph (0, 0)][DBLP]
    ICVS, 2001, pp:220-235 [Conf]
  27. Walid A. Najjar, Lucas Roh, A. P. Wim Böhm
    The Initial Performance of a Bottom-Up Clustering Algorithm for Dataflow Graphs. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:91-100 [Conf]
  28. Lucas Roh, Walid A. Najjar, Bhanu Shankar, A. P. Wim Böhm
    An Evaluation of Optimized Threaded Code Generation. [Citation Graph (0, 0)][DBLP]
    IFIP PACT, 1994, pp:37-46 [Conf]
  29. Jeffrey Hammes, A. P. Wim Böhm, Charlie Ross, Monica Chawathe, Bruce A. Draper, Robert Rinker, Walid A. Najjar
    Loop fusion and temporal common subexpression elimination in window-based loops. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:142- [Conf]
  30. Dianne R. Kumar, Walid A. Najjar, Pradip K. Srimani
    Performance Evaluation of a New Hardware Supported Multicast Scheme for K-ary N-cubes. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:160- [Conf]
  31. Walid A. Najjar, William Marcus Miller, A. P. Wim Böhm
    An Analysis of Loop Latency in Dataflow Execution. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:352-360 [Conf]
  32. Chuanjun Zhang, Frank Vahid, Walid A. Najjar
    A Highly-Configurable Cache Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:136-146 [Conf]
  33. Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar
    A tunable bus encoder for off-chip data buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:319-322 [Conf]
  34. Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar
    A way-halting cache for low-energy high-performance systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:126-131 [Conf]
  35. Chuanjun Zhang, Frank Vahid, Walid A. Najjar
    Energy Benefits of a Configurable Line Size Cache for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:87-91 [Conf]
  36. Zhi Guo, Betul Buyukkurt, Walid A. Najjar
    Input data reuse in compiling window operations onto reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    LCTES, 2004, pp:249-256 [Conf]
  37. Dinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, Greg Stitt
    Profiling tools for hardware/software partitioning of embedded applications. [Citation Graph (0, 0)][DBLP]
    LCTES, 2003, pp:189-198 [Conf]
  38. Annette Lagman, Walid A. Najjar
    Analysis of Buffer Design for Adaptive Routing in Direct Networks. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 1996, pp:134-139 [Conf]
  39. Walid A. Najjar, Annette Lagman, Sumit Sur, Pradip K. Srimani
    Modeling Adaptive Routing in k-ary n-cube Networks. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 1994, pp:120-125 [Conf]
  40. Walid A. Najjar, Jean-Luc Gaudiot
    Reliability and Performance Modelling of Hypercube-Based Mutliprocessors. [Citation Graph (0, 0)][DBLP]
    Computer Performance and Reliability, 1987, pp:305-320 [Conf]
  41. A. P. Wim Böhm, Walid A. Najjar, Bhanu Shankar, Lucas Roh
    An evaluation of bottom-up and top-down thread generation techniques. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:118-127 [Conf]
  42. William Marcus Miller, Walid A. Najjar, A. P. Wim Böhm
    A Quantitative Analysis of Locality in Dataflow Programs. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:12-18 [Conf]
  43. Lucas Roh, Walid A. Najjar
    Design of storage hierarchy in multithreaded architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:271-278 [Conf]
  44. Paraskevas Evripidou, Walid A. Najjar, Jean-Luc Gaudiot
    A Single-Assignment Language in a Distributed Memory Multiprocessor. [Citation Graph (0, 0)][DBLP]
    PARLE (2), 1989, pp:304-320 [Conf]
  45. Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, A. Mitra, Anirban Banerjee, Walid A. Najjar
    Towards In-Situ Data Storage in Sensor Databases. [Citation Graph (0, 0)][DBLP]
    Panhellenic Conference on Informatics, 2005, pp:36-46 [Conf]
  46. Dianne Miller, Walid A. Najjar
    Preliminary Evaluation of a Hybrid Deterministic/Adaptive Router. [Citation Graph (0, 0)][DBLP]
    PCRCW, 1997, pp:89-102 [Conf]
  47. Jeffrey Hammes, Robert Rinker, A. P. Wim Böhm, Walid A. Najjar, Bruce A. Draper
    A High Level, Algorithmic Programming Language and Compiler for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  48. Dinesh C. Suresh, Walid A. Najjar, Jun Yang
    Power Efficient Instruction Caches for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:182-191 [Conf]
  49. Anirban Banerjee, A. Mitra, Walid A. Najjar
    Splitting the sensor node. [Citation Graph (0, 0)][DBLP]
    SenSys, 2005, pp:270-271 [Conf]
  50. Walid A. Najjar, Jean-Luc Gaudiot
    A data-driven execution paradigm for distributed fault-tolerance. [Citation Graph (0, 0)][DBLP]
    ACM SIGOPS European Workshop, 1990, pp:- [Conf]
  51. Annette Lagman, Walid A. Najjar, Sumit Sur, Pradip K. Srimani
    Evaluation of Idealized Adaptive Routing on k-ary n-cubes. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:166-169 [Conf]
  52. Walid A. Najjar, Jean-Luc Gaudiot
    Limits on Scalability in Gracefully Degradable Large-Scale Systems. [Citation Graph (0, 0)][DBLP]
    Symposium on Reliable Distributed Systems, 1989, pp:148-157 [Conf]
  53. Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar
    A Way-Halting Cache for Low-Energy High-Performance Systems. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2003, v:2, n:, pp:- [Journal]
  54. Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper, Jeffrey Hammes, Robert Rinker, J. Ross Beveridge, Monica Chawathe, Charles Ross
    High-Level Language Abstraction for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:8, pp:63-69 [Journal]
  55. William Marcus Miller, Walid A. Najjar, A. P. Wim Böhm
    Exploiting Data Structure Locality in the Dataflow Model. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:27, n:2, pp:183-200 [Journal]
  56. Walid A. Najjar, A. P. Wim Böhm, William Marcus Miller
    A Quantitative Analysis of Dataflow Program Execution - Preliminaries to a Hybrid Design. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1993, v:18, n:3, pp:314-326 [Journal]
  57. Lucas Roh, Walid A. Najjar, Bhanu Shankar, A. P. Wim Böhm
    Generation, Optimization, and Evaluation of Multithreaded Code. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1996, v:32, n:2, pp:188-204 [Journal]
  58. Lucas Roh, Bhanu Shankar, A. P. Wim Böhm, Walid A. Najjar
    Resource Management in Dataflow-Based Multithreaded Execution. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2001, v:61, n:5, pp:581-608 [Journal]
  59. Walid A. Najjar, Edward A. Lee, Guang R. Gao
    Advances in the dataflow computational model. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1999, v:25, n:13-14, pp:1907-1929 [Journal]
  60. Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar
    A way-halting cache for low-energy high-performance systems. [Citation Graph (0, 0)][DBLP]
    TACO, 2005, v:2, n:1, pp:34-54 [Journal]
  61. Dianne R. Kumar, Walid A. Najjar, Pradip K. Srimani
    A New Adaptive Hardware Tree-Based Multicast Routing in K-Ary N-Cubes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:7, pp:647-659 [Journal]
  62. Annette Lagman, Walid A. Najjar, Pradip K. Srimani
    An Analysis of Edge Fault Tolerance in Recursively Decomposable Regular Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:4, pp:470-475 [Journal]
  63. Walid A. Najjar, Jean-Luc Gaudiot
    Network Resilience: A Measure of Network Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:2, pp:174-181 [Journal]
  64. Walid A. Najjar, Jean-Luc Gaudiot
    Authors' Reply. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:12, pp:1452-1453 [Journal]
  65. Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm, Jeffrey Hammes
    Automatic compilation to a coarse-grained reconfigurable system-opn-chip. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:4, pp:560-589 [Journal]
  66. Chuanjun Zhang, Frank Vahid, Walid A. Najjar
    A highly configurable cache for low energy embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:2, pp:363-387 [Journal]
  67. A. P. Wim Böhm, Jeffrey Hammes, Bruce A. Draper, Monica Chawathe, Charlie Ross, Robert Rinker, Walid A. Najjar
    Mapping a Single Assignment Programming Language to Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2002, v:21, n:2, pp:117-130 [Journal]
  68. Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi
    Compile-time area estimation for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:104-122 [Journal]
  69. Song Lin, Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar
    Efficient indexing data structures for flash-based sensor devices. [Citation Graph (0, 0)][DBLP]
    TOS, 2006, v:2, n:4, pp:468-503 [Journal]
  70. Walid A. Najjar
    Compiling code accelerators for FPGAs. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:1-2 [Conf]
  71. Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros
    A one-shot configurable-cache tuner for improved energy and performance. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:755-760 [Conf]
  72. Zhi Guo, Walid A. Najjar
    A Compiler Intermediate Representation for Reconfigurable Fabrics. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  73. Zhi Guo, Abhishek Mitra, Walid A. Najjar
    Automation of IP Core Interface Generation for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  74. Dinesh C. Suresh, Zhi Guo, Betul Buyukkurt, Walid A. Najjar
    Automatic Compilation Framework for Bloom Filter Based Intrusion Detection. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:413-418 [Conf]
  75. Betul Buyukkurt, Zhi Guo, Walid A. Najjar
    Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:401-412 [Conf]
  76. Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers
    Optimized Generation of Data-Path from C Codes for FPGAs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  77. Robert Rinker, M. Carter, A. Patel, Monica Chawathe, Charlie Ross, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm
    An automated process for compiling dataflow graphs into reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:130-139 [Journal]

  78. Boosting XML filtering through a scalable FPGA-based architecture. [Citation Graph (, )][DBLP]


  79. Compiling code accelerators for FPGAs. [Citation Graph (, )][DBLP]


  80. Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System. [Citation Graph (, )][DBLP]


  81. Compiled hardware acceleration of Molecular Dynamics code. [Citation Graph (, )][DBLP]


  82. Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs. [Citation Graph (, )][DBLP]


  83. Accelerating XML Query Matching through Custom Stack Generation on FPGAs. [Citation Graph (, )][DBLP]


  84. Dynamic Co-Processor Architecture for Software Acceleration on CSoCs. [Citation Graph (, )][DBLP]


  85. Reconfigurable Computing in the New Age of Parallelism. [Citation Graph (, )][DBLP]


  86. Compiling PCRE to FPGA for accelerating SNORT IDS. [Citation Graph (, )][DBLP]


  87. Boosting XML Filtering with a Scalable FPGA-based Architecture [Citation Graph (, )][DBLP]


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