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Publications of Author

1. Olivier Muller, Amer Baghdadi, Michel Jézéquel
   ASIP-based multiprocessor SoC design for simple and double binary turbo decoding. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:1330-1335 [Conf]
   
2. Matthieu Arzel, Cyril Lahuec, Fabrice Seguin, David Gnaedig, Michel Jézéquel
   . Analog slice turbo decoding. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2005, pp:332-335 [Conf]
   
3. Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel
   A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2006, pp:430-431 [Conf]
   
4. Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel
   Design, Implementation and Prototyping of a Flexible Architecture Dedicated to Block Turbo Decoding. [Citation Graph (0, 0)][DBLP]
   ReCoSoC, 2006, pp:152-159 [Conf]
   
5. David Gnaedig, Emmanuel Boutillon, Michel Jézéquel, Vincent C. Gaudet, P. Glenn Gulak
   On Multiple Slice Turbo Codes. [Citation Graph (0, 0)][DBLP]
   Annales des Télécommunications, 2005, v:60, n:1-2, pp:79-102 [Journal]
   
6. Ramesh Pyndiah, Michel Jézéquel
   Foreword / Éditorial. [Citation Graph (0, 0)][DBLP]
   Annales des Télécommunications, 2005, v:60, n:1-2, pp:6-9 [Journal]
   
7. Hazem Moussa, Olivier Muller, Amer Baghdadi, Michel Jézéquel
   Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding. [Citation Graph (0, 0)][DBLP]
   DATE, 2007, pp:654-659 [Conf]
   
8. Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel
   Towards Gb/s turbo decoding of product code onto an FPGA device. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:909-912 [Conf]
   
9. Erwan Piriou, Christophe Jégo, Patrick Adde, R. Le Bidan, Michel Jézéquel
   Efficient architecture for Reed Solomon block turbo code. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
10. Matthieu Arzel, Fabrice Seguin, Cyril Lahuec, Michel Jézéquel
    Semi-iterative analog turbo decoding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
11. Olivier Muller, Amer Baghdadi, Michel Jézéquel
    On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference. [Citation Graph (0, 0)][DBLP]
    GLOBECOM, 2006, pp:- [Conf]
    
12. 
    Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder. [Citation Graph (, )][DBLP]
    
    
13. 
    ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications. [Citation Graph (, )][DBLP]
    
    
14. 
    Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm. [Citation Graph (, )][DBLP]
    
    
15. 
    Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder. [Citation Graph (, )][DBLP]
    
    
16. 
    From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding. [Citation Graph (, )][DBLP]
    
    
17. 
    Rapid Prototyping of ASIP-based Flexible MMSE-IC Linear Equalizer. [Citation Graph (, )][DBLP]
    
    
18. 
    Energy Efficient Turbo Decoder with Reduced State Metric Quantization. [Citation Graph (, )][DBLP]
    
    
19. 
    A highly parallel Turbo Product Code decoder without interleaving resource. [Citation Graph (, )][DBLP]