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Publications of Author

1. N. Venkateswaran, V. Barath Kumar, R. Raghavan, R. Srinivas, S. Subramanian, V. Balaji, V. Mahalingam, T. L. Rajaprabhu
   Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design. [Citation Graph (0, 0)][DBLP]
   DELTA, 2004, pp:333-340 [Conf]
   
2. N. Venkateswaran, Krishna Bharath
   Frequency Domain Testing of General Purpose Processors at the Instruction Execution Level. [Citation Graph (0, 0)][DBLP]
   DELTA, 2004, pp:15-22 [Conf]
   
3. N. Venkateswaran, C. Chandramouli
   General Purpose Processor Architecture for Modeling Stochastic Biological Neuronal Assemblies. [Citation Graph (0, 0)][DBLP]
   ICES, 2003, pp:387-397 [Conf]
   
4. N. Venkateswaran, V. Balaji, V. Mahalingam, T. L. Rajaprabhu
   Analysis of Bit Transition Count for EDAC Encoded FSM. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2003, pp:166- [Conf]
   
5. S. Rahul, J. Vignesh, S. Santhosh Kumar, M. Bharadwaj, N. Venkateswaran
   Comparison of Pyramidal and Packet Wavelet Coder for Image Compression Using Cellular Neural Network (CNN) with Thresholding and Quantization. [Citation Graph (0, 0)][DBLP]
   ITNG, 2007, pp:183-184 [Conf]
   
6. N. Venkateswaran, S. Pattabiraman, R. Devanathan, B. Kumaran, Ashraf Ahmed, Sankara Narayanan, Radharamanan
   A Design Methodology for Very Large Array Processors - Part 1: Gipop Processor Array. [Citation Graph (0, 0)][DBLP]
   IJPRAI, 1995, v:9, n:2, pp:231-262 [Journal]
   
7. N. Venkateswaran, S. Pattabiraman, J. DeSouza, G. Sriram, R. Srinivasan, R. Sankar, G. Suresh
   A Design Methodology for Very Large Array Processors - Part 2: Pacube VLSI Arrays. [Citation Graph (0, 0)][DBLP]
   IJPRAI, 1995, v:9, n:2, pp:263-301 [Journal]
   
8. N. Venkateswaran, S. Balaji, V. Sridhar
   Fault tolerant bus architecture for deep submicron based processors. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2005, v:33, n:1, pp:148-155 [Journal]
   
9. Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, J. Piaget, N. Venkateswaran, Jeffrey G. Hemmett
   First-Order Incremental Block-Based Statistical Timing Analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2170-2180 [Journal]
   
10. 
    On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system. [Citation Graph (, )][DBLP]
    
    
11. 
    A Frequency Adaptive Packet Wavelet Coder for Still Images Using CNN. [Citation Graph (, )][DBLP]