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## Search the dblp DataBase
Chandramouli Visweswariah:
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## Publications of Author- Xiaoliang Bai, Chandramouli Visweswariah, Philip N. Strenski
**Uncertainty-aware circuit optimization.**[Citation Graph (0, 0)][DBLP] DAC, 2002, pp:58-63 [Conf] - Andrew R. Conn, Ibrahim M. Elfadel, W. W. Molzen, P. R. O'Brien, Philip N. Strenski, Chandramouli Visweswariah, C. B. Whan
**Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation.**[Citation Graph (0, 0)][DBLP] DAC, 1999, pp:452-459 [Conf] - Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah
**Is statistical timing statistically significant?**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:498- [Conf] - Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
**Statistical timing for parametric yield prediction of digital integrated circuits.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:932-937 [Conf] - Chandramouli Visweswariah, Rakesh Chadha, Chin-Fu Chen
**Model Development and Verification for High Level Analog Blocks.**[Citation Graph (0, 0)][DBLP] DAC, 1988, pp:376-382 [Conf] - Chandramouli Visweswariah, Ronald A. Rohrer
**Efficient Simulation of Bipolar Digital ICs.**[Citation Graph (0, 0)][DBLP] DAC, 1991, pp:32-37 [Conf] - Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan
**First-order incremental block-based statistical timing analysis.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:331-336 [Conf] - Chandramouli Visweswariah, Jalal A. Wehbeh
**Incremental Event-Driven Simulation of Digital FET Circuits.**[Citation Graph (0, 0)][DBLP] DAC, 1993, pp:737-741 [Conf] - Daniel Brand, Chandramouli Visweswariah
**Inaccuracies in power estimation during logic synthesis.**[Citation Graph (0, 0)][DBLP] ICCAD, 1996, pp:388-394 [Conf] - Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah
**Optimization of custom MOS circuits by transistor sizing.**[Citation Graph (0, 0)][DBLP] ICCAD, 1996, pp:174-180 [Conf] - Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah
**Noise considerations in circuit optimization.**[Citation Graph (0, 0)][DBLP] ICCAD, 1998, pp:220-227 [Conf] - Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah, Chai Wah Wu
**Circuit optimization via adjoint Lagrangians.**[Citation Graph (0, 0)][DBLP] ICCAD, 1997, pp:281-288 [Conf] - Chandramouli Visweswariah
**Optimization techniques for high-performance digital circuits.**[Citation Graph (0, 0)][DBLP] ICCAD, 1997, pp:198-205 [Conf] - Chandramouli Visweswariah, Andrew R. Conn
**Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation.**[Citation Graph (0, 0)][DBLP] ICCAD, 1999, pp:244-252 [Conf] - Chandramouli Visweswariah, Peter Feldmann, Ronald A. Rohrer
**Incorporation of Inductors in Piecewise Approximate Circuit Simulation.**[Citation Graph (0, 0)][DBLP] ICCAD, 1990, pp:162-165 [Conf] - Andrew R. Conn, Chandramouli Visweswariah
**Overview of continuous optimization advances and applications to circuit tuning.**[Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:74-81 [Conf] - Andreas Wächter, Chandramouli Visweswariah, Andrew R. Conn
**Large-scale nonlinear optimization in circuit tuning.**[Citation Graph (0, 0)][DBLP] Future Generation Comp. Syst., 2005, v:21, n:8, pp:1251-1262 [Journal] - Rakesh Chadha, Chandramouli Visweswariah, Chin-Fu Chen
**M**[Citation Graph (0, 0)][DBLP]^{3}-a multilevel mixed-mode mixed A/D simulator. IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:575-585 [Journal] - Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah, Chai Wah Wu
**JiffyTune: circuit optimization using time-domain sensitivities.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1292-1309 [Journal] - Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
**Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2376-2392 [Journal] - Chandramouli Visweswariah, Ruud A. Haring, Andrew R. Conn
**Noise considerations in circuit optimization.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:6, pp:679-690 [Journal] - Chandramouli Visweswariah, Ronald A. Rohrer
**Piecewise approximate circuit simulation.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:861-870 [Journal] - Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, J. Piaget, N. Venkateswaran, Jeffrey G. Hemmett
**First-Order Incremental Block-Based Statistical Timing Analysis.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2170-2180 [Journal]
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