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Publications of Author

1. Friederich Kupzog, Holger Blume, Tobias G. Noll, Kieran McLaughlin, Sakir Sezer, John McCanny
   Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup. [Citation Graph (0, 0)][DBLP]
   AICT/ICIW, 2006, pp:56- [Conf]
   
2. Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh
   Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality. [Citation Graph (0, 0)][DBLP]
   ASAP, 2000, pp:66-0 [Conf]
   
3. Holger Blume, H. Hübert, H. T. Feldkämper, Tobias G. Noll
   Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip. [Citation Graph (0, 0)][DBLP]
   ASAP, 2002, pp:29-40 [Conf]
   
4. Thorsten von Sydow, B. Neumann, Holger Blume, Tobias G. Noll
   Quantitative Analysis of Embedded FPGA-Architectures for Arithmetic. [Citation Graph (0, 0)][DBLP]
   ASAP, 2006, pp:125-131 [Conf]
   
5. Hans-Martin Blüthgen, Patrick Osterloh, Holger Blume, Tobias G. Noll
   A Hardware Implementation for Approximate Text Search in Multimedia Applications. [Citation Graph (0, 0)][DBLP]
   IEEE International Conference on Multimedia and Expo (III), 2000, pp:1425-1428 [Conf]
   
6. Kieran McLaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias G. Noll, John McCanny
   Design and analysis of matching circuit architectures for a closest match lookup. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2006, pp:- [Conf]
   
7. Holger Blume, Daniel Becker, Martin Botteck, Jörg Brakensiek, Tobias G. Noll
   Hybrid Functional and Instruction Level Power Modeling for Embedded Processors. [Citation Graph (0, 0)][DBLP]
   SAMOS, 2006, pp:216-226 [Conf]
   
8. Holger Blume, Thorsten von Sydow, Daniel Becker, Tobias G. Noll
   Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets. [Citation Graph (0, 0)][DBLP]
   SAMOS, 2005, pp:374-383 [Conf]
   
9. Holger Blume, Thorsten von Sydow, Tobias G. Noll
   Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets. [Citation Graph (0, 0)][DBLP]
   SAMOS, 2004, pp:484-493 [Conf]
   
10. Holger Blume, Jörg von Livonius, Lisa Rotenberg, Tobias G. Noll, Harald Bothe, Jörg Brakensiek
    Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:74-81 [Conf]
    
11. Holger Blume, Daniel Becker, Lisa Rotenberg, Martin Botteck, Jörg Brakensiek, Tobias G. Noll
    Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:10, pp:689-702 [Journal]
    
12. Holger Blume, Thorsten von Sydow, Daniel Becker, Tobias G. Noll
    Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:8, pp:466-476 [Journal]
    
13. Holger Blume, Thorsten von Sydow, Tobias G. Noll
    A Case Study for the Application of Deterministic and Stochastic Petri Nets in the SoC Communication Domain. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:43, n:2-3, pp:223-233 [Journal]
    
14. 
    Konstruktion und Etablierung einer Klimakammer für die Untersuchung der embryonalen Herzentwicklung. [Citation Graph (, )][DBLP]
    
    
15. 
    Design flow for embedded FPGAs based on a flexible architecture template. [Citation Graph (, )][DBLP]
    
    
16. 
    A Power Estimation Model for an FPGA-based Softcore Processor. [Citation Graph (, )][DBLP]
    
    
17. 
    Programmable Architectures for Realtime Music Decompression. [Citation Graph (, )][DBLP]
    
    
18. 
    ASIP-eFPGA Architecture for Multioperable GNSS Receivers. [Citation Graph (, )][DBLP]
    
    
19. 
    Perceptual feature based music classification - A DSP perspective for a new type of application. [Citation Graph (, )][DBLP]
    
    
20. 
    Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures. [Citation Graph (, )][DBLP]
    
    
21. 
    Design of a Pareto-optimization environment and its application to motion estimation. [Citation Graph (, )][DBLP]