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Marisa López-Vallejo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pablo Ituero, Marisa López-Vallejo
    New Schemes in Clustered VLIW Processors Applied to Turbo Decoding. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:291-296 [Conf]
  2. José Luis Ayala, Marisa Lópes-Vallejo
    Compiler-Driven Power Optimizations in the Register File of Processor-Based Systems. [Citation Graph (0, 0)][DBLP]
    Power-aware Computing Systems, 2005, pp:- [Conf]
  3. David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo
    Compiler-Driven Leakage Energy Reduction in Banked Register Files. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:107-116 [Conf]
  4. Pablo Ituero, Gorka Landaburu, Javier Del Ser, Marisa López-Vallejo, Pedro M. Crespo, Vicente Atxa, Jon Altuna
    Joint Source-Channel Decoding ASIP Architecture for Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ICESS, 2007, pp:98-108 [Conf]
  5. Pablo Ituero, José L. Ayala, Marisa López-Vallejo
    Leakage-based On-Chip Thermal Sensor for CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3327-3330 [Conf]
  6. Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo
    Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:121-124 [Conf]

  7. Thermal Characterization and Thermal Management in Processor-Based Systems. [Citation Graph (, )][DBLP]


  8. A Web-Based Environment Providing Remote Access To FPGA Platforms For Teaching Digital Hardware Design. [Citation Graph (, )][DBLP]


  9. An FPGA run-time parameterisable Log-Normal Random Number Generator. [Citation Graph (, )][DBLP]


  10. Designing Highly Parameterized Hardware using xHdl. [Citation Graph (, )][DBLP]


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