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David Atienza: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. José Manuel Velasco, David Atienza, Francky Catthoor, Francisco Tirado, Katzalin Olcoz, Jose Manuel Mendias
    Garbage Collector Refinement for New Dynamic Multimedia Applications on Embedded Systems. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2004, pp:25-32 [Conf]
  2. David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias
    A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:618-623 [Conf]
  3. Francesco Poletti, Paul Marchal, David Atienza, Luca Benini, Francky Catthoor, Jose Manuel Mendias
    An integrated hardware/software approach for run-time scratchpad management. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:238-243 [Conf]
  4. Srinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli
    A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:845-848 [Conf]
  5. David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris
    Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:532-537 [Conf]
  6. Alexandros Bartzas, Stylianos Mamagkakis, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
    Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:740-745 [Conf]
  7. Nicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, Francky Catthoor
    A Complete Network-On-Chip Emulation Framework. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:246-251 [Conf]
  8. Stylianos Mamagkakis, David Atienza, Christophe Poucet, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias
    Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:874-875 [Conf]
  9. Stylianos Mamagkakis, David Atienza, Christophe Poucet, Francky Catthoor, Dimitrios Soudris
    Energy-efficient dynamic memory allocators at the middleware level of embedded systems. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2006, pp:215-222 [Conf]
  10. David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris
    Reducing memory accesses with a system-level design methodology in customized dynamic memory management. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2004, pp:93-98 [Conf]
  11. Salvatore Carta, Andrea Acquaviva, Pablo Garcia Del Valle, David Atienza, Giovanni De Micheli, Fernando Rincón, Luca Benini, Jose Manuel Mendias
    Multi-processor operating system emulation framework with thermal feedback for systems-on-chip. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:311-316 [Conf]
  12. Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Designing application-specific networks on chips with floorplan information. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:355-362 [Conf]
  13. David Atienza, Marc Leeman, Francky Catthoor, Geert Deconinck, Jose Manuel Mendias, Vincenzo De Florio, Rudy Lauwereins
    Fast prototyping and refinement of complex dynamic data types in multimedia applications for consumer embedded devices. [Citation Graph (0, 0)][DBLP]
    ICME, 2004, pp:803-806 [Conf]
  14. Nicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Román Hermida, Francky Catthoor
    A novel approach for network on chip emulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2365-2368 [Conf]
  15. Marc Leeman, Chantal Ykman, David Atienza, Vincenzo De Florio, Geert Deconinck
    Automated Dynamic Memory Data Type Implementation Exploration and Optimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:222-224 [Conf]
  16. Nicolas Genko, David Atienza, Giovanni De Micheli
    Exploration and Tuning of Custom NoC Topologies Using an FPGA-Based Framework. [Citation Graph (0, 0)][DBLP]
    PARCO, 2005, pp:753-760 [Conf]
  17. J. B. Pérez-Ramas, David Atienza, M. Peón, Ivan Magan, Jose Manuel Mendias, Román Hermida
    Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs. [Citation Graph (0, 0)][DBLP]
    PARCO, 2005, pp:769-776 [Conf]
  18. José Manuel Velasco, David Atienza, Katzalin Olcoz, Francky Catthoor
    Performance Evaluation of Barrier Techniques for Distributed Tracing Garbage Collectors. [Citation Graph (0, 0)][DBLP]
    PARCO, 2005, pp:549-556 [Conf]
  19. David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris
    Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:510-520 [Conf]
  20. David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo
    Compiler-Driven Leakage Energy Reduction in Banked Register Files. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:107-116 [Conf]
  21. Marc Leeman, David Atienza, Francky Catthoor, Vincenzo De Florio, Geert Deconinck, Jose Manuel Mendias, Rudy Lauwereins
    Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:289-298 [Conf]
  22. José Manuel Velasco, David Atienza, Katzalin Olcoz, Francky Catthoor, Francisco Tirado, Jose Manuel Mendias
    Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:69-78 [Conf]
  23. Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, José M. Mendías, Antonios Thanailakis
    Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications. [Citation Graph (0, 0)][DBLP]
    WWIC, 2005, pp:354-364 [Conf]
  24. Stylianos Mamagkakis, Alexandros Mpartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias, Antonios Thanailakis
    Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology. [Citation Graph (0, 0)][DBLP]
    WWIC, 2004, pp:26-37 [Conf]
  25. Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
    Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 2006, v:29, n:13-14, pp:2612-2620 [Journal]
  26. David Atienza, Stylianos Mamagkakis, Francesco Poletti, Jose Manuel Mendias, Francky Catthoor, Luca Benini, Dimitrios Soudris
    Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:2, pp:113-130 [Journal]
  27. David Atienza, Jose Manuel Mendias, Stylianos Mamagkakis, Dimitrios Soudris, Francky Catthoor
    Systematic dynamic memory management design methodology for reduced memory footprint. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:465-489 [Journal]
  28. Edgar G. Daylight, David Atienza, Arnout Vandecappelle, Francky Catthoor, José M. Mendías
    Memory-access-aware data structure transformations for embedded software with dynamic data accesses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:269-280 [Journal]
  29. Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli
    Interactive presentation: Improving the fault tolerance of nanometric PLA designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:570-575 [Conf]
  30. Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo
    Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:121-124 [Conf]
  31. Alexandros Bartzas, M. Peón, Stylianos Mamagkakis, David Atienza, F. Catthoort, Dimitrios Soudris, M. Mendias
    Systematic design flow for dynamic data management in visual texture decoder of MPEG-4. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  32. Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli
    Early wire characterization for predictable network-on-chip global interconnects. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:57-64 [Conf]
  33. Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:158-163 [Conf]
  34. Pablo Garcia Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini, Giovanni De Micheli
    A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:140-145 [Conf]
  35. Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini
    NoC Design and Implementation in 65nm Technology. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:273-282 [Conf]
  36. Stylianos Mamagkakis, Alexandros Bartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
    Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:7, pp:417-436 [Journal]
  37. Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini
    Bringing NoCs to 65 nm. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:5, pp:75-85 [Journal]
  38. David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida
    HW-SW emulation framework for temperature-aware design in MPSoCs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]
  39. Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:869-880 [Journal]

  40. A control theory approach for thermal balancing of MPSoC. [Citation Graph (, )][DBLP]


  41. A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories. [Citation Graph (, )][DBLP]


  42. Reliability-aware design for nanometer-scale devices. [Citation Graph (, )][DBLP]


  43. Temperature-aware processor frequency assignment for MPSoCs using convex optimization. [Citation Graph (, )][DBLP]


  44. Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems. [Citation Graph (, )][DBLP]


  45. Programmable logic circuits based on ambipolar CNFET. [Citation Graph (, )][DBLP]


  46. Thermal-aware data flow analysis. [Citation Graph (, )][DBLP]


  47. Thermal Characterization and Thermal Management in Processor-Based Systems. [Citation Graph (, )][DBLP]


  48. Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization. [Citation Graph (, )][DBLP]


  49. Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures. [Citation Graph (, )][DBLP]


  50. OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  51. Dynamic thermal management in 3D multicore architectures. [Citation Graph (, )][DBLP]


  52. Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis. [Citation Graph (, )][DBLP]


  53. Evaluation and design exploration of solar harvested-energy prediction algorithm. [Citation Graph (, )][DBLP]


  54. Energy-efficient variable-flow liquid cooling in 3D stacked architectures. [Citation Graph (, )][DBLP]


  55. Design Flow of Dynamically-Allocated Data Types in Embedded Applications Based on Elitist Evolutionary Computation Optimization. [Citation Graph (, )][DBLP]


  56. Analysis of multi-objective evolutionary algorithms to optimize dynamic data types in embedded systems. [Citation Graph (, )][DBLP]


  57. Mixed heuristic and mathematical programming using reference points for dynamic data types optimization in multimedia embedded systems. [Citation Graph (, )][DBLP]


  58. Optimization of dynamic memory managers for embedded systems using grammatical evolution. [Citation Graph (, )][DBLP]


  59. Improving reliability of embedded systems through dynamic memory manager optimization using grammatical evolution. [Citation Graph (, )][DBLP]


  60. Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems. [Citation Graph (, )][DBLP]


  61. Thermal-aware compilation for system-on-chip processing architectures. [Citation Graph (, )][DBLP]


  62. Online convex optimization-based algorithm for thermal management of MPSoCs. [Citation Graph (, )][DBLP]


  63. Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays. [Citation Graph (, )][DBLP]


  64. Reliability Support for On-Chip Memories Using Networks-on-Chip. [Citation Graph (, )][DBLP]


  65. Template-Based Semi-Automatic Profiling of Multimedia Applications. [Citation Graph (, )][DBLP]


  66. Efficient Object Placement including Node Selection in a Distributed Virtual Machine. [Citation Graph (, )][DBLP]


  67. Systematic intermediate sequence removal for reduced memory accesses. [Citation Graph (, )][DBLP]


  68. Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation. [Citation Graph (, )][DBLP]


  69. Wavelet-Based ECG Delineation on a Wearable Embedded Sensor Platform. [Citation Graph (, )][DBLP]


  70. Implementation of an Automated ECG-based Diagnosis Algorithm for a Wireless Body Sensor Plataform. [Citation Graph (, )][DBLP]


  71. Through Silicon Via-Based Grid for Thermal Control in 3D Chips. [Citation Graph (, )][DBLP]


  72. Scalable instruction set simulator for thousand-core architectures running on GPGPUs. [Citation Graph (, )][DBLP]


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