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Publications of Author

1. V. R. Devanathan
   Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2005, pp:300-305 [Conf]
   
2. D. Janaki Ram, M. A. Maluk Mohamed, V. R. Devanathan
   A Framework for Concurrency Control in Real-Time Distributed Collaboration for Mobile Systems. [Citation Graph (0, 0)][DBLP]
   ICDCS Workshops, 2003, pp:488-492 [Conf]
   
3. C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar
   A Framework for Distributed and Hierarchical Design-for-Test. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2005, pp:497-503 [Conf]
   
4. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
   Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2007, pp:351-356 [Conf]
   
5. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
   Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. [Citation Graph (0, 0)][DBLP]
   VTS, 2007, pp:167-172 [Conf]
   
6. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
   Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. [Citation Graph (0, 0)][DBLP]
   DATE, 2007, pp:534-539 [Conf]
   
7. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
   On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:3, pp:464-476 [Journal]
   
8. 
   Methodology for low power test pattern generation using activity threshold control logic. [Citation Graph (, )][DBLP]
   
   
9. 
   Variation-Tolerant, Power-Safe Pattern Generation. [Citation Graph (, )][DBLP]