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V. Kamakoti: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti
    A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:791-794 [Conf]
  2. Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti
    A function generator-based reconfigurable system. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:905-909 [Conf]
  3. E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
    Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1200-1203 [Conf]
  4. K. Uday Bhaskar, M. Prasanth, V. Kamakoti, Kailasnath Maneparambil
    A Framework for Automatic Assembly Program Generator (A2PG) for Verification and Testing of Processor Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:40-45 [Conf]
  5. L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti
    A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:262-267 [Conf]
  6. Thomas Graf, V. Kamakoti, N. S. Janaki Latha, C. Pandu Rangan
    The Colored Sector Search Tree: A Dynamic Data Structure for Efficient High Dimensional Nearest-Foreign-Neighbor Queries. [Citation Graph (0, 0)][DBLP]
    COCOON, 1998, pp:35-44 [Conf]
  7. V. Kamakoti, Kamala Krithivasan, C. Pandu Rangan
    Efficient Randomized Incremental Algorithm For The Closest Pair Problem Using Leafary Trees. [Citation Graph (0, 0)][DBLP]
    COCOON, 1995, pp:71-80 [Conf]
  8. A. Manoj Kumar, Jayaram Bobba, V. Kamakoti
    MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:922-929 [Conf]
  9. Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti
    FPGA based Agile Algorithm-On-Demand Co-Processor. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:82-83 [Conf]
  10. A. Manoj Kumar, B. Jayaram, V. Kamakoti
    SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:251- [Conf]
  11. E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
    Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:265- [Conf]
  12. L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti
    Testable Clock Routing Architecture for Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1044-1047 [Conf]
  13. R. Manimegalai, A. Manoj Kumar, B. Jayaram, V. Kamakoti
    MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1185- [Conf]
  14. K. Najeeb, Vishal Gupta, V. Kamakoti
    Delay and peak power minimization for on-chip buses using temporal redundancy. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:119-122 [Conf]
  15. B. Jayaram, A. Manoj Kumar, V. Kamakoti
    Parallel Partitioning Techniques for Logic Minimization Using Redundancy Identification. [Citation Graph (0, 0)][DBLP]
    HiPC, 2003, pp:174-183 [Conf]
  16. A. Pavan Kumar, Sukhendu Das, V. Kamakoti
    Face Recognition Using Weighted Modular Principle Component Analysis. [Citation Graph (0, 0)][DBLP]
    ICONIP, 2004, pp:362-367 [Conf]
  17. Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti
    A Hardware-Directed Face Recognition System Based on Local Eigen-analysis with PCNN. [Citation Graph (0, 0)][DBLP]
    ICONIP, 2004, pp:327-332 [Conf]
  18. V. Kamakoti, N. Balakrishnan
    Efficient Algorithms for Prefix and General Prefix Computations on Distributed Shared Memory Systems with Applications. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1997, pp:44-51 [Conf]
  19. A. Pavan Kumar, V. Kamakoti, Sukhendu Das
    An Architecture for Real Time Face Recognition Using WMPCA. [Citation Graph (0, 0)][DBLP]
    ICVGIP, 2004, pp:644-649 [Conf]
  20. P. Jagan Mohan, V. Kamakoti, C. Pandu Rangan
    Efficient Randomized Parallel Algorithm for the Closest Pair Problem in D-dimension. [Citation Graph (0, 0)][DBLP]
    IFIP Congress (1), 1994, pp:547-552 [Conf]
  21. Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, S. Suresh, V. Ganesh, V. Kamakoti
    A Parallel Evolutionary Approach to Spatial Partitioning in Reconfigurable Environments. [Citation Graph (0, 0)][DBLP]
    IICAI, 2003, pp:938-951 [Conf]
  22. K. Srinathan, C. Pandu Rangan, V. Kamakoti
    Toward Optimal Player Weights in Secure Distributed Protocols. [Citation Graph (0, 0)][DBLP]
    INDOCRYPT, 2001, pp:232-241 [Conf]
  23. Siva Nageswara Rao Borra, Annamalai Muthukaruppan, S. Suresh, V. Kamakoti
    A Parallel Genetic Approach to the Placement Problem for Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:184- [Conf]
  24. A. Manoj Kumar, B. Jayaram, R. Manimegalai, V. Kamakoti
    MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  25. E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
    Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  26. M. Madhu, V. Srinivasa Murty, V. Kamakoti
    Dynamic Coding Technique For Low-Power Data Bus. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:252-253 [Conf]
  27. Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, S. Suresh, V. Kamakoti
    An Evolutionary Algorithm for Automatic Spatial Partitioning in Reconfigurable Environments. [Citation Graph (0, 0)][DBLP]
    MICAI, 2004, pp:735-745 [Conf]
  28. L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti, Sivaprakasam Suresh
    On-Line Location of Multiple Faults in LUT Based Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:224-232 [Conf]
  29. K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti
    A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:207-212 [Conf]
  30. Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti
    An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:507-510 [Conf]
  31. R. Manimegalai, E. Siva Soumya, V. Muralidharan, Balaraman Ravindran, V. Kamakoti, D. Bhatia
    Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:451-456 [Conf]
  32. Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti
    A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:795-798 [Conf]
  33. E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
    Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:736-741 [Conf]
  34. Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, V. Bala Kuteshwar
    A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:1071-1076 [Conf]
  35. Kavish Seth, K. N. Viswajith, S. Srinivasan, V. Kamakoti
    Ultra Folded High-Speed Architectures for Reed-Solomon Decoders. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:517-520 [Conf]
  36. P. Subrahmanya, R. Manimegalai, V. Kamakoti, Madhu Mutyam
    A Bus Encoding Technique for Power and Cross-talk Minimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:443-448 [Conf]
  37. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
    Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:351-356 [Conf]
  38. K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula
    Controllability-driven Power Virus Generation for Digital Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:407-412 [Conf]
  39. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
    Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:167-172 [Conf]
  40. K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula
    Power Virus Generation Using Behavioral Models of Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:35-42 [Conf]
  41. Siva Nageswara Rao Borra, Annamalai Muthukaruppan, S. Suresh, V. Kamakoti
    A novel approach to the placement and routing problems for field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    Appl. Soft Comput., 2007, v:7, n:1, pp:455-470 [Journal]
  42. Thomas Graf, V. Kamakoti
    Sparse Dominance Queries for Many Points in Optimal Time and Space. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1997, v:64, n:6, pp:287-291 [Journal]
  43. V. Kamakoti, C. Pandu Rangan
    An Optimal Algorithm for Reconstructing a Binary Tree. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1992, v:42, n:2, pp:113-115 [Journal]
  44. K. Arvind, V. Kamakoti, C. Pandu Rangan
    Efficient Parallel Algorithms for Permutation Graphs. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:26, n:1, pp:116-124 [Journal]
  45. V. Kamakoti, Kamala Krithivasan, C. Pandu Rangan
    An Efficient Randomized Algorithm for the Closest Pair Problem on Colored Point Sets. [Citation Graph (0, 0)][DBLP]
    Nord. J. Comput., 1995, v:2, n:1, pp:28-40 [Journal]
  46. V. Annamalai, C. S. Krishnamoorthy, V. Kamakoti
    Adaptive finite element analysis on a parallel and distributed environment. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1999, v:25, n:12, pp:1413-1434 [Journal]
  47. A. Pavan Kumar, V. Kamakoti, Sukhendu Das
    System-on-programmable-chip implementation for on-line face recognition. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition Letters, 2007, v:28, n:3, pp:342-349 [Journal]
  48. L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti
    Pseudo-online testing methodologies for various components of field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:2-3, pp:99-119 [Journal]
  49. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
    Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:534-539 [Conf]
  50. Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti
    FPGA based Agile Algorithm-On-Demand Co-Processor [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  51. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
    On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:464-476 [Journal]
  52. K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam
    Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:425-436 [Journal]

  53. Efficient Grouping of Fail Chips for Volume Yield Diagnostics. [Citation Graph (, )][DBLP]


  54. Impact of Temperature on Test Quality. [Citation Graph (, )][DBLP]


  55. Hardware based genetic evolution of self-adaptive arbitrary response FIR filters. [Citation Graph (, )][DBLP]


  56. Variation-Tolerant, Power-Safe Pattern Generation. [Citation Graph (, )][DBLP]


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