|
Search the dblp DataBase
Gerolf Hoflehner:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- R. David Weldon, Steven S. Chang, Hong Wang, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen
Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. [Citation Graph (0, 0)][DBLP] Interaction between Compilers and Computer Architectures, 2002, pp:57-67 [Conf]
- Alex Settle, Daniel A. Connors, Gerolf Hoflehner, Daniel M. Lavery
Optimization for the Intel® Itanium ®Architectur Register Stack. [Citation Graph (0, 0)][DBLP] CGO, 2003, pp:115-124 [Conf]
- Gerolf Hoflehner, Knud Kirkegaard, Rod Skinner, Daniel M. Lavery, Yong-Fong Lee, Wei Li
Compiler Optimizations for Transaction Processing Workloads on Itanium® Linux Systems. [Citation Graph (0, 0)][DBLP] MICRO, 2004, pp:294-303 [Conf]
- Shih-wei Liao, Perry H. Wang, Hong Wang, John Paul Shen, Gerolf Hoflehner, Daniel M. Lavery
Post-Pass Binary Adaptation for Software-Based Speculative Precomputation. [Citation Graph (0, 0)][DBLP] PLDI, 2002, pp:117-128 [Conf]
- Gerolf Hoflehner, Daniel M. Lavery, David C. Sehr
The compiler as a validation and evaluation tool. [Citation Graph (0, 0)][DBLP] Electr. Notes Theor. Comput. Sci., 2003, v:82, n:2, pp:- [Journal]
- Jay Bharadwaj, William Y. Chen, Weihaw Chuang, Gerolf Hoflehner, Kishore N. Menezes, Kalyan Muthukumar, Jim Pierce
The Intel IA-64 Compiler Code Generator. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2000, v:20, n:5, pp:44-53 [Journal]
- Gerolf Hoflehner, Darshan Desai, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum
Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture. [Citation Graph (0, 0)][DBLP] SIGMETRICS, 2007, pp:361-362 [Conf]
Strategies for Predicate-Aware Register Allocation. [Citation Graph (, )][DBLP]
Performance Characterization of Itanium® 2-Based Montecito Processor. [Citation Graph (, )][DBLP]
Search in 0.028secs, Finished in 0.029secs
|