|
Search the dblp DataBase
Kishore N. Menezes:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Kishore N. Menezes, Sumedh W. Sathaye, Thomas M. Conte
Path Prediction for High Issue-Rate Processors. [Citation Graph (0, 0)][DBLP] IEEE PACT, 1997, pp:178-188 [Conf]
- Emre Özer, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte
A Fast Interrupt Handling Scheme for VLIW Processors. [Citation Graph (0, 0)][DBLP] IEEE PACT, 1998, pp:136-141 [Conf]
- Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye
A technique to determine power-efficient, high-performance superscalar processors. [Citation Graph (0, 0)][DBLP] HICSS (1), 1995, pp:324-333 [Conf]
- Thomas M. Conte, Mary Ann Hirsch, Kishore N. Menezes
Reducing State Loss For Effective Trace Sampling of Superscalar Processors. [Citation Graph (0, 0)][DBLP] ICCD, 1996, pp:468-477 [Conf]
- Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills, Burzin A. Patel
Optimization of Instruction Fetch Mechanisms for High Issue Rates. [Citation Graph (0, 0)][DBLP] ISCA, 1995, pp:333-344 [Conf]
- Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye
Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. [Citation Graph (0, 0)][DBLP] MICRO, 1996, pp:201-211 [Conf]
- Thomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch
Accurate and Practical Profile-driven Compilation Using the Profile Buffer. [Citation Graph (0, 0)][DBLP] MICRO, 1996, pp:36-45 [Conf]
- Jay Bharadwaj, Kishore N. Menezes, Chris McKinsey
Wavefront Scheduling: Path based Data Representation and Scheduling of Subgraphs. [Citation Graph (0, 0)][DBLP] MICRO, 1999, pp:262-271 [Conf]
- Jay Bharadwaj, Kishore N. Menezes, Chris McKinsey
Wavefront Scheduling: Path Based Data Representation and Scheduling of Subgraphs. [Citation Graph (0, 0)][DBLP] J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
- Jay Bharadwaj, William Y. Chen, Weihaw Chuang, Gerolf Hoflehner, Kishore N. Menezes, Kalyan Muthukumar, Jim Pierce
The Intel IA-64 Compiler Code Generator. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2000, v:20, n:5, pp:44-53 [Journal]
- Sanjeev Banerjia, Sumedh W. Sathaye, Kishore N. Menezes, Thomas M. Conte
MPS: Miss-Path Scheduling for Multiple-Issue Processors. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1998, v:47, n:12, pp:1382-1397 [Journal]
- Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen
System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:129-137 [Journal]
Search in 0.000secs, Finished in 0.001secs
|