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Robert Rinker: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jeffrey Hammes, Robert Rinker, A. P. Wim Böhm, Walid A. Najjar, Bruce A. Draper, J. Ross Beveridge
    Cameron: High level Language Compilation for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:236-244 [Conf]
  2. Robert Rinker, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper
    Compiling Image Processing Applications to Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:56-65 [Conf]
  3. Bruce A. Draper, Walid A. Najjar, A. P. Wim Böhm, Jeffrey Hammes, Robert Rinker, Charlie Ross, Monica Chawathe, José Bins
    Compiling and Optimizing Image Processing Algorithms for FPGAs. [Citation Graph (0, 0)][DBLP]
    CAMP, 2000, pp:222-231 [Conf]
  4. Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi
    Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:239-0 [Conf]
  5. Jeffrey Hammes, A. P. Wim Böhm, Charlie Ross, Monica Chawathe, Bruce A. Draper, Robert Rinker, Walid A. Najjar
    Loop fusion and temporal common subexpression elimination in window-based loops. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:142- [Conf]
  6. Jeffrey Hammes, Robert Rinker, A. P. Wim Böhm, Walid A. Najjar, Bruce A. Draper
    A High Level, Algorithmic Programming Language and Compiler for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  7. Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper, Jeffrey Hammes, Robert Rinker, J. Ross Beveridge, Monica Chawathe, Charles Ross
    High-Level Language Abstraction for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:8, pp:63-69 [Journal]
  8. A. P. Wim Böhm, Jeffrey Hammes, Bruce A. Draper, Monica Chawathe, Charlie Ross, Robert Rinker, Walid A. Najjar
    Mapping a Single Assignment Programming Language to Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2002, v:21, n:2, pp:117-130 [Journal]
  9. Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi
    Compile-time area estimation for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:104-122 [Journal]
  10. Robert Rinker, M. Carter, A. Patel, Monica Chawathe, Charlie Ross, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm
    An automated process for compiling dataflow graphs into reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:130-139 [Journal]

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