Journals in DBLP

IEEE Trans. VLSI Syst.
2001, volume: 9, number: 1

1. Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Stammermann, Arne Schulz, E. Macii, Wolfgang Nebel
   Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:3-14 [Journal]
   
2. Tajana Simunic, Luca Benini, Giovanni De Micheli
   Energy-efficient design of battery-powered embedded systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:15-28 [Journal]
   
3. Thomas L. Martin, Daniel P. Siewiorek
   Nonideal battery and main memory effects on CPU speed-setting for low power. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:29-34 [Journal]
   
4. Oliver Yuk-Hang Leung, Chi-Ying Tsui, R. S.-K. Cheng
   Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltage. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:34-41 [Journal]
   
5. Khurram Muhammad, Robert B. Staszewski, Poras T. Balsara
   Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:42-51 [Journal]
   
6. Suhwan Kim, Marios C. Papaefthymiou
   True single-phase adiabatic circuitry. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:52-63 [Journal]
   
7. Scott Meninger, Jose Oscar Mur-Miranda, Rajeevan Amirtharajah, Anantha Chandrakasan, J. H. Lang
   Vibration-to-electric energy conversion. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:64-76 [Journal]
   
8. Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, N. Vijaykumar
   Reducing leakage in a high-performance deep-submicron instruction cache. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:77-89 [Journal]
   
9. Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul
   Robust subthreshold logic for ultra-low power operation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:90-99 [Journal]
   
10. F. Svelto, S. Deantoni, G. Montagna, R. Castello
    Implementation of a CMOS LNA plus mixer for GPS applications with no external components. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:100-104 [Journal]
    
11. Benjamin Bishop, V. Lyuboslavsky, Narayanan Vijaykrishnan, Mary Jane Irwin
    Design considerations for databus charge recovery. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:104-106 [Journal]
    
12. R. Vemuri, R. K. Gupta
    Guest editorial reconfigurable and adaptive VLSI systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:107-108 [Journal]
    
13. Takayuki Suyama, Makoto Yokoo, Hiroshi Sawada, Akira Nagoya
    Solving satisfiability problems using reconfigurable computing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:109-116 [Journal]
    
14. Fatih Kocan, Daniel G. Saab
    ATPG for combinational circuits on configurable hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:117-129 [Journal]
    
15. Robert Rinker, M. Carter, A. Patel, Monica Chawathe, Charlie Ross, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm
    An automated process for compiling dataflow graphs into reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:130-139 [Journal]
    
16. V. Srinivasan, S. Govindarajan, R. Vemuri
    Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:140-158 [Journal]
    
17. Miron Abramovici, Charles E. Stroud
    BIST-based test and diagnosis of FPGA logic blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:159-172 [Journal]
    
18. Rafael Maestre, F. Kurdahl, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh
    A formal approach to context scheduling for multicontext reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:173-185 [Journal]
    
19. Silviu M. S. A. Chiricescu, Miriam Leeser, Mankuan Michael Vai
    Design and analysis of a dynamically reconfigurable three-dimensional FPGA. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:186-196 [Journal]
    
20. Philip Heng Wai Leong, C. W. Sham, W. C. Wong, H. Y. Wong, Wing Seung Yuen, Monk-Ping Leong
    A bitstream reconfigurable FPGA implementation of the WSAT algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:197-201 [Journal]
    
21. Brad L. Hutchings, Brent E. Nelson
    Unifying simulation and execution in a design environment for FPGA systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:201-205 [Journal]
    
22. Oskar Mencer, Marco Platzner, Martin Morf, Michael J. Flynn
    Object-oriented domain specific compilers for programming FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:205-210 [Journal]
    
23. E. Cantó, Juan Manuel Moreno, Joan Cabestany, I. Lacadena, Josep Maria Insenser
    A temporal bipartitioning algorithm for dynamically reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:210-218 [Journal]
    
24. Andrew A. Duncan, David C. Hendry, Peter Gray
    The COBRA-ABS high-level synthesis system for multi-FPGA custom computing machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:218-223 [Journal]
    
25. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
    Structural analysis and generation of synthetic digital circuits with memory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:223-226 [Journal]
    
26. Adrian Stoica, R. Zebulum, Didier Keymeulen, Raoul Tawel, Taher Daud, Anil Thakoor
    Reconfigurable VLSI architectures for evolvable hardware: from experimental field programmable transistor arrays to evolution-oriented chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:227-232 [Journal]