The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Philip H. Sweany: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jason Hiser, Steve Carr, Philip H. Sweany
    Global Register Partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:13-23 [Conf]
  2. Yi Qian, Steve Carr, Philip H. Sweany
    Optimizing Loop Performance for Clustered VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:271-280 [Conf]
  3. Wentong Li, Krishna M. Kavi, Afrin Naz, Philip H. Sweany
    Speculative Thread Execution in a Multithreaded Dataflow Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2006, pp:102-107 [Conf]
  4. Afrin Naz, Krishna M. Kavi, Philip H. Sweany, Wentong Li
    A Study of Reconfigurable Split Data Caches and Instruction Caches. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2006, pp:235-240 [Conf]
  5. Steve Carr, Philip H. Sweany
    Automatic data partitioning for the agere payload plus network processor. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:238-247 [Conf]
  6. Chen Ding, Steve Carr, Philip H. Sweany
    Modulo Scheduling with Cache Reuse Information. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1997, pp:1079-1083 [Conf]
  7. Michael J. Bourke III, Philip H. Sweany, Steven J. Beaty
    Extending List Scheduling to Consider Execution Frequency. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1996, pp:193-202 [Conf]
  8. Steve Carr, Chen Ding, Philip H. Sweany
    Improving Software Pipelining with Unroll-and-Jam. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1996, pp:183-192 [Conf]
  9. Afrin Naz, Krishna M. Kavi, Philip H. Sweany, Mehran Rezaei
    A Study of Separate Array and Scalar Caches. [Citation Graph (0, 0)][DBLP]
    HPCS, 2004, pp:157-164 [Conf]
  10. Jason Hiser, Steve Carr, Philip H. Sweany, Steven J. Beaty
    Register Assignment for Software Pipelining with Partitioned Register Banks. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:211-218 [Conf]
  11. Xianglong Huang, Steve Carr, Philip H. Sweany
    Loop Transformations for Architectures with Partitioned Register Banks. [Citation Graph (0, 0)][DBLP]
    LCTES/OM, 2001, pp:48-55 [Conf]
  12. Yi Qian, Steve Carr, Philip H. Sweany
    Loop fusion for clustered VLIW architectures. [Citation Graph (0, 0)][DBLP]
    LCTES-SCOPES, 2002, pp:112-119 [Conf]
  13. Michael A. Howland, Robert A. Mueller, Philip H. Sweany
    Trace scheduling optimization in a retargetable microcode compiler. [Citation Graph (0, 0)][DBLP]
    MICRO, 1987, pp:106-114 [Conf]
  14. Philip H. Sweany, Steven J. Beaty
    Post-compaction register assignment in a retargetable compiler. [Citation Graph (0, 0)][DBLP]
    MICRO, 1990, pp:107-116 [Conf]
  15. Philip H. Sweany, Steven J. Beaty
    Dominator-path scheduling: a global scheduling method. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:260-263 [Conf]
  16. Philip H. Sweany, Steve Carr, Brett L. Huber
    Compiler Optimization for Superscalar Systems: Global Instruction Scheduling without Copies. [Citation Graph (0, 0)][DBLP]
    Digital Technical Journal, 1998, v:10, n:1, pp:- [Journal]
  17. Afrin Naz, Mehran Rezaei, Krishna M. Kavi, Philip H. Sweany
    Improving data cache performance with integrated use of split caches, victim cache and stream buffers. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:41-48 [Journal]
  18. Vicki H. Allan, Steven J. Beaty, Bogong Su, Philip H. Sweany
    Building a Retargetable Local Instruction Scheduler. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1998, v:28, n:3, pp:249-283 [Journal]
  19. Steve Carr, Philip H. Sweany
    An experimental evaluation of scalar replacement on scientific benchmarks. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 2003, v:33, n:15, pp:1419-1445 [Journal]
  20. Robert A. Mueller, Michael R. Duda, Philip H. Sweany, Jack S. Walicki
    Horizon: A Retargetable Compiler for Horizontal Microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1988, v:14, n:5, pp:575-583 [Journal]
  21. Jian Huang, Hao Li, Philip H. Sweany
    An FPGA implementation of elliptic curve cryptography for future secure web transaction. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2007, pp:296-301 [Conf]

Search in 0.005secs, Finished in 0.007secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002