Journals in DBLP

IEEE Trans. Computers
1992, volume: 41, number: 12

1. Milos D. Ercegovac, Tomás Lang
   On-the-Fly Rounding. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:12, pp:1497-1503 [Journal]
   
2. Divyakant Agrawal, Jonathan R. Agre
   Recovering from Multiple Process Failures in the Time Warp Mechanism. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:12, pp:1504-1514 [Journal]
   
3. Gwan S. Choi, Ravishankar K. Iyer
   FOCUS: An Experimental Environment for Fault Sensitivity Analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:12, pp:1515-1526 [Journal]
   
4. Franz Fink, Karl Fuchs, Michael H. Schulz
   Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:12, pp:1527-1536 [Journal]
   
5. Wen-mei W. Hwu, Pohua P. Chang
   Efficient Instruction Sequencing with Inline Target Insertion. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:12, pp:1537-1551 [Journal]
   
6. Trevor G. Clarkson, Denise Gorse, John G. Taylor, C. K. Ng
   Learning Probabilistic RAM Nets Using VLSI Structures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:12, pp:1552-1561 [Journal]
   
7. Andrzej Hlawiczka
   Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:12, pp:1562-1571 [Journal]
   
8. Ramesh Krishnamurti
   An Approximation Algorithm for Scheduling Tasks on Varying Partition Sizes in Partitionable Multiprocessor Systems. [Citation Graph (1, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:12, pp:1572-1579 [Journal]
   
9. Rohit Kapur, M. Ray Mercer
   Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:12, pp:1580-1588 [Journal]
   
10. Matthew T. O'Keefe, José A. B. Fortes, Benjamin W. Wah
    On the Relationship Between Two Systolic Array Design Mehodologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:12, pp:1589-1593 [Journal]
    
11. Graham M. Megson
    A Fast Faddeev Array. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:12, pp:1594-1600 [Journal]
    
12. Bella Bose, Sulaiman Al-Bassam
    Byte Unidirectional Error Correcting and Detecting Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:12, pp:1601-1606 [Journal]
    
13. Paolo Montuschi, Luigi Ciminiera
    Design of a Radix 4 Division Unit with Simple Selection Table. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:12, pp:1606-1611 [Journal]
    
14. Nhon T. Quach, Michael J. Flynn
    High-Speed Addition in CMOS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:12, pp:1612-1615 [Journal]
    
15. Sy-Yen Kuo, Sheng-Chiech Liang
    Concurrent Error Detection and Correction in Real-Time Systolic Sorting Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:12, pp:1615-1620 [Journal]
    
16. Ahmed E. Kamal
    An Algorithm for the Efficient Utilization of Bandwidth in the Slotted Ring. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:12, pp:1620-1627 [Journal]
    
17. Eric J. Schwabe
    A Benes-like Theorem for the Shuffle-Exchange Graph. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:12, pp:1627-1630 [Journal]