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Wen-mei W. Hwu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Brian L. Deitrich, Ben-Chung Cheng, Wen-mei W. Hwu
    Improving Static Branch Prediction in a Compiler. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:214-221 [Conf]
  2. Erik M. Nystrom, Ronald D. Barnes, Matthew C. Merten, Wen-mei W. Hwu
    Code Reordering and Speculation Support for Dynamic Optimization System. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:163-174 [Conf]
  3. David M. Gallagher, William Y. Chen, Scott A. Mahlke, John C. Gyllenhaal, Wen-mei W. Hwu
    Dynamic Memory Disambiguation Using the Memory Conflict Buffer. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1994, pp:183-193 [Conf]
  4. Daniel A. Connors, Hillery C. Hunter, Ben-Chung Cheng, Wen-mei W. Hwu
    Hardware Support for Dynamic Management of Compiler-Directed Computation Reuse. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2000, pp:222-233 [Conf]
  5. Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker
    Sentinel Scheduling for VLIW and Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1992, pp:238-247 [Conf]
  6. Hillery C. Hunter, Wen-mei W. Hwu
    Code coverage and input variability: effects on architecture and compiler research. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:79-87 [Conf]
  7. Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Chein Chen, Jiajuin Wei
    Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1986, pp:254-258 [Conf]
  8. Daniel A. Connors, Jean-Michel Puiatti, David I. August, Kevin M. Crozier, Wen-mei W. Hwu
    An Architecture Framework for Introducing Predicated Execution into Embedded Microprocessors. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:1301-1311 [Conf]
  9. Neal J. Alewine, Shyh-Kwei Chen, Chung-Chi Jim Li, W. Kent Fuchs, Wen-mei W. Hwu
    Branch Recovery with Compiler-Assisted Multiple Instruction Retry. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:66-73 [Conf]
  10. Roger A. Bringmann, Scott A. Mahlke, Wen-mei W. Hwu
    A study of the effects of compiler-controlled speculation on instruction and data caches. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1995, pp:211-220 [Conf]
  11. David I. August, Daniel A. Connors, John C. Gyllenhaal, Wen-mei W. Hwu
    Architectural Support for Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:84-93 [Conf]
  12. Wen-mei W. Hwu, Sanjay J. Patel
    The Future of Computer Architecture Research: An Industrial Perspective. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:264- [Conf]
  13. W. Kent Fuchs, Wen-mei W. Hwu, Neal J. Alewine
    Application of Compiler-Assisted Rollback Recovery to Speculative Execution Repair. [Citation Graph (0, 0)][DBLP]
    Hardware and Software Architectures for Fault Tolerance, 1993, pp:45-65 [Conf]
  14. Sadun Anik, Wen-mei W. Hwu
    Executing Nested Parallel Loops on Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1992, pp:241-244 [Conf]
  15. Shyh-Kwei Chen, W. Kent Fuchs, Wen-mei W. Hwu
    An Analytical Approach to Scheduling Code for Superscalar and VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1994, pp:285-292 [Conf]
  16. William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu
    Tolerating First Level Memory Access Latency in High-Performance Systems. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1992, pp:36-43 [Conf]
  17. Scott A. Mahlke, Nancy J. Warter, William Y. Chen, Pohua P. Chang, Wen-mei W. Hwu
    The Effect of Compiler Optimizations on Available Parallelism in Scalar Programs. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1991, pp:142-145 [Conf]
  18. William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu, Tokuzo Kiyohara, Pohua P. Chang
    Tolerating data access latency with register preloading. [Citation Graph (0, 0)][DBLP]
    ICS, 1992, pp:104-113 [Conf]
  19. Pohua P. Chang, Wen-mei W. Hwu
    Control flow optimization for supercomputer scalar processing. [Citation Graph (0, 0)][DBLP]
    ICS, 1989, pp:145-153 [Conf]
  20. Jeffrey P. Monks, Vaduvur Bharghavan, Wen-mei W. Hwu
    A Power Controlled Multiple Access Protocol for Wireless Packet Networks. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2001, pp:219-228 [Conf]
  21. David I. August, Daniel A. Connors, Scott A. Mahlke, John W. Sias, Kevin M. Crozier, Ben-Chung Cheng, Patrick R. Eaton, Qudus B. Olaniran, Wen-mei W. Hwu
    Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:227-237 [Conf]
  22. David I. August, John W. Sias, Jean-Michel Puiatti, Scott A. Mahlke, Daniel A. Connors, Kevin M. Crozier, Wen-mei W. Hwu
    The Program Decision Logic Approach to Predicated Execution. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:208-219 [Conf]
  23. Wen-mei W. Hwu
    Retrospective: IMPACT: An Architectural Framework for Multiple-Instruction Issue. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:77-79 [Conf]
  24. Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu
    IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:266-275 [Conf]
  25. Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu
    IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:408-417 [Conf]
  26. Wen-mei W. Hwu, Pohua P. Chang
    Exploiting Parallel Microprocessor Microarchitectures With a Compiler Code Generator. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:45-53 [Conf]
  27. Wen-mei W. Hwu, Pohua P. Chang
    Achieving High Instruction Cache Performance with an Optimizing Compiler. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:242-251 [Conf]
  28. Wen-mei W. Hwu, Thomas M. Conte, Pohua P. Chang
    Comparing Software and Hardware Schemes For Reducing the Cost of Branches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:224-233 [Conf]
  29. Wen-mei W. Hwu, Yale N. Patt
    HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:297-306 [Conf]
  30. Wen-mei W. Hwu, Yale N. Patt
    Checkpoint Repair for Out-of-order Execution Machines. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:18-26 [Conf]
  31. Wen-mei W. Hwu, Yale N. Patt
    Retrospective: HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:43-44 [Conf]
  32. Wen-mei W. Hwu, Yale N. Patt
    HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:300-308 [Conf]
  33. Teresa L. Johnson, Wen-mei W. Hwu
    Run-Time Adaptive Cache Hierarchy Management via Reference Analysis. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:315-326 [Conf]
  34. Tokuzo Kiyohara, Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Sadun Anik, Wen-mei W. Hwu
    Register Connection: A New Approach to Adding Registers into Instruction Set Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:247-256 [Conf]
  35. Scott A. Mahlke, Richard E. Hank, James E. McCormick, David I. August, Wen-mei W. Hwu
    A Comparison of Full and Partial Predicated Execution Support for ILP Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:138-150 [Conf]
  36. Matthew C. Merten, Andrew R. Trick, Christopher N. George, John C. Gyllenhaal, Wen-mei W. Hwu
    A Hardware-Driven Profiling Scheme for Identifying Program Hot Spots to Support Runtime Optimization. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:136-147 [Conf]
  37. Matthew C. Merten, Andrew R. Trick, Erik M. Nystrom, Ronald D. Barnes, Wen-mei W. Hwu
    A hardware mechanism for dynamic extraction and relayout of program hot spots. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:59-70 [Conf]
  38. John W. Sias, Sain-zee Ueng, Geoff A. Kent, Ian M. Steiner, Erik M. Nystrom, Wen-mei W. Hwu
    Field-testing IMPACT EPIC research results in Itanium 2. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:26-39 [Conf]
  39. Jeffrey P. Monks, Vaduvur Bharghavan, Wen-mei W. Hwu
    Transmission Power Control for Multiple Access Wireless Packet Networks. [Citation Graph (0, 0)][DBLP]
    LCN, 2000, pp:12-21 [Conf]
  40. Jeffrey P. Monks, Jean-Pierre Ebert, Adam Wolisz, Wen-mei W. Hwu
    A Study of the Energy Saving and Capacity Improvement Potential of Power Control in Multi-Hop Wireless Networks. [Citation Graph (0, 0)][DBLP]
    LCN, 2001, pp:550-559 [Conf]
  41. Lakshmi N. Chakrapani, John C. Gyllenhaal, Wen-mei W. Hwu, Scott A. Mahlke, Krishna V. Palem, Rodric M. Rabbah
    Trimaran: An Infrastructure for Research in Instruction-Level Parallelism. [Citation Graph (0, 0)][DBLP]
    LCPC, 2004, pp:32-41 [Conf]
  42. William Y. Chen, Roger A. Bringmann, Scott A. Mahlke, Sadun Anik, Tokuzo Kiyohara, Nancy J. Warter, Daniel M. Lavery, Wen-mei W. Hwu, Richard E. Hank, John C. Gyllenhaal
    Using Profile Information to Assist Advaced Compiler Optimization and Scheduling. [Citation Graph (0, 0)][DBLP]
    LCPC, 1992, pp:31-48 [Conf]
  43. Ben-Chung Cheng, Wen-mei W. Hwu
    An Empirical Study of Function Pointers Using SPEC Benchmarks. [Citation Graph (0, 0)][DBLP]
    LCPC, 1999, pp:490-493 [Conf]
  44. Daniel A. Connors, Wen-mei W. Hwu
    Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:158-169 [Conf]
  45. Roger A. Bringmann, Scott A. Mahlke, Richard E. Hank, John C. Gyllenhaal, Wen-mei W. Hwu
    Speculative execution exception recovery using write-back suppression. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:214-223 [Conf]
  46. David I. August, Wen-mei W. Hwu, Scott A. Mahlke
    A Framework for Balancing Control Flow and Predication. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:92-103 [Conf]
  47. Pohua P. Chang, William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu
    Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:25-33 [Conf]
  48. Pohua P. Chang, Wen-mei W. Hwu
    Trace selection for compiling large C application programs to microcode. [Citation Graph (0, 0)][DBLP]
    MICRO, 1988, pp:21-29 [Conf]
  49. P.-H. Chang, Wen-mei W. Hwu
    Forward semantic: a compiler-assisted instruction fetch method for heavily pipelined processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1989, pp:188-198 [Conf]
  50. Ronald D. Barnes, Erik M. Nystrom, Matthew C. Merten, Wen-mei W. Hwu
    Vacuum packing: extracting hardware-detected program phases for post-link optimization. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:233-244 [Conf]
  51. Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu
    Beating in-order stalls with "flea-flicker" two-pass pipelining. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:387-398 [Conf]
  52. Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu
    "Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:319-330 [Conf]
  53. William Y. Chen, Scott A. Mahlke, Pohua P. Chang, Wen-mei W. Hwu
    Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:69-73 [Conf]
  54. Ben-Chung Cheng, Daniel A. Connors, Wen-mei W. Hwu
    Compiler-Directed Early Load-Address Generation. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:138-147 [Conf]
  55. Brian L. Deitrich, Wen-mei W. Hwu
    Speculative Hedge: Regulating Compile-time Speculation Against Profile Variations. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:70-79 [Conf]
  56. Wen-mei W. Hwu, Yale N. Patt
    Exploiting horizontal and vertical concurrency via the HPSm microprocessor. [Citation Graph (0, 0)][DBLP]
    MICRO, 1987, pp:154-161 [Conf]
  57. Teresa L. Johnson, Matthew C. Merten, Wen-mei W. Hwu
    Run-Time Spatial Locality Detection and Optimization. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:57-64 [Conf]
  58. John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau
    Optimization of Machine Descriptions for Efficient Use. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:349-358 [Conf]
  59. Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau
    Region-based compilation: an introduction and motivation. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:158-168 [Conf]
  60. Richard E. Hank, Scott A. Mahlke, Roger A. Bringmann, John C. Gyllenhaal, Wen-mei W. Hwu
    Superblock formation using static program analysis. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:247-255 [Conf]
  61. Cheng-Hsueh A. Hsieh, John C. Gyllenhaal, Wen-mei W. Hwu
    Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:90-99 [Conf]
  62. Daniel M. Lavery, Wen-mei W. Hwu
    Unrolling-based optimizations for modulo scheduling. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:327-337 [Conf]
  63. Daniel M. Lavery, Wen-mei W. Hwu
    Modulo Scheduling of Loops in Control-intensive Non-numeric Programs. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:126-137 [Conf]
  64. Scott A. Mahlke, Richard E. Hank, Roger A. Bringmann, John C. Gyllenhaal, David M. Gallagher, Wen-mei W. Hwu
    Characterizing the impact of predicated execution on branch prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:217-227 [Conf]
  65. Matthew C. Merten, Wen-mei W. Hwu
    Modulo schedule buffers. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:138-149 [Conf]
  66. John W. Sias, Wen-mei W. Hwu, David I. August
    Accurate and efficient predicate analysis with binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:112-123 [Conf]
  67. John W. Sias, Hillery C. Hunter, Wen-mei W. Hwu
    Enhancing loop buffering of media and telecommunications applications using low-overhead predication. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:262-273 [Conf]
  68. Yoji Yamada, John Gyllenhall, Grant Haab, Wen-mei W. Hwu
    Data relocation and prefetching for programs with large data sets. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:118-127 [Conf]
  69. James E. Wilson, Stephen W. Melvin, Michael Shebanow, Wen-mei W. Hwu, Yale N. Patt
    On tuning the microarchitecture of an HPS implementation of the VAX. [Citation Graph (0, 0)][DBLP]
    MICRO, 1987, pp:162-167 [Conf]
  70. Erik M. Nystrom, Hong-Seok Kim, Wen-mei W. Hwu
    Importance of heap specialization in pointer analysis. [Citation Graph (0, 0)][DBLP]
    PASTE, 2004, pp:43-48 [Conf]
  71. Ben-Chung Cheng, Wen-mei W. Hwu
    Modular interprocedural pointer analysis using access paths: design, implementation, and evaluation. [Citation Graph (0, 0)][DBLP]
    PLDI, 2000, pp:57-69 [Conf]
  72. Wen-mei W. Hwu, Pohua P. Chang
    Inline Function Expansion for Compiling C Programs. [Citation Graph (0, 0)][DBLP]
    PLDI, 1989, pp:246-257 [Conf]
  73. Nancy J. Warter, Scott A. Mahlke, Wen-mei W. Hwu, B. Ramakrishna Rau
    Reverse If-Conversion. [Citation Graph (0, 0)][DBLP]
    PLDI, 1993, pp:290-299 [Conf]
  74. Le-Chun Wu, Rajiv Mirani, Harish Patil, Bruce Olsen, Wen-mei W. Hwu
    A New Framework for Debugging Globally Optimized Code. [Citation Graph (0, 0)][DBLP]
    PLDI, 1999, pp:181-191 [Conf]
  75. Erik M. Nystrom, Hong-Seok Kim, Wen-mei W. Hwu
    Bottom-Up and Top-Down Context-Sensitive Summary-Based Pointer Analysis. [Citation Graph (0, 0)][DBLP]
    SAS, 2004, pp:165-180 [Conf]
  76. Scott A. Mahlke, William Y. Chen, John C. Gyllenhaal, Wen-mei W. Hwu
    Compiler Code Transformations for Superscalar-Based High Performance Systems. [Citation Graph (0, 0)][DBLP]
    SC, 1992, pp:808-817 [Conf]
  77. Aloke Gupta, Wen-mei W. Hwu
    Xprof: Profiling the Execution of X Window Programs. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1992, pp:253-254 [Conf]
  78. Wen-mei W. Hwu, Thomas M. Conte
    A Simulation Study of Simultaneous Vector Prefetch Performance in Multiprocessor Memory Subsystems (Extended Abstract). [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1989, pp:227- [Conf]
  79. Thomas M. Conte, Wen-mei W. Hwu
    Advances in Benchmarking Techniques: New Standards and Quantitative Metrics. [Citation Graph (0, 0)][DBLP]
    Advances in Computers, 1995, v:41, n:, pp:231-253 [Journal]
  80. Jeffrey P. Monks, Jean-Pierre Ebert, Wen-mei W. Hwu, Adam Wolisz
    Energy saving and capacity improvement potential of power control in multi-hop wireless networks. [Citation Graph (0, 0)][DBLP]
    Computer Networks, 2003, v:41, n:3, pp:313-330 [Journal]
  81. Wen-mei W. Hwu
    Introduction to Predicate Execution. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1998, v:31, n:, pp:49-50 [Journal]
  82. Thomas M. Conte, Wen-mei W. Hwu
    Benchmark Characterization. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1991, v:24, n:1, pp:48-56 [Journal]
  83. Cheng-Hsueh A. Hsieh, Marie T. Conte, Teresa L. Johnson, John C. Gyllenhaal, Wen-mei W. Hwu
    Optimizing NET Compilers for Improved Java Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:6, pp:67-75 [Journal]
  84. John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau
    Optimization of Machine Descriptions for Efficient Use. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1998, v:26, n:4, pp:417-447 [Journal]
  85. David I. August, Wen-mei W. Hwu, Scott A. Mahlke
    The Partial Reverse If-Conversion Framework for Balancing Control Flow and Predication. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1999, v:27, n:5, pp:381-423 [Journal]
  86. Steve Beaty, Wen-mei W. Hwu
    Foreword to the Special Issue. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1998, v:26, n:4, pp:345-347 [Journal]
  87. Thomas M. Conte, Wen-mei W. Hwu, Mark Smotherman
    Editor's Introduction. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1999, v:27, n:5, pp:325-326 [Journal]
  88. Thomas M. Conte, Wen-mei W. Hwu, Mark Smotherman
    Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1999, v:27, n:6, pp:425-426 [Journal]
  89. Sadun Anik, Wen-mei W. Hwu
    Performance Implications of Synchronization Support for Parallel Fortran Programs. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1994, v:22, n:2, pp:202-215 [Journal]
  90. Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu
    Tolerating Cache-Miss Latency with Multipass Pipelines. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:40-47 [Journal]
  91. Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu
    Profile-guided Automatic Inline Expansion for C Programs. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1992, v:22, n:5, pp:349-369 [Journal]
  92. Pohua P. Chang, Scott A. Mahlke, Wen-mei W. Hwu
    Using Profile Information to Assist Classic Code Optimizations. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1991, v:21, n:12, pp:1301-1321 [Journal]
  93. Shyh-Kwei Chen, Neal J. Alewine, W. Kent Fuchs, Wen-mei W. Hwu
    Incremental Compiler Transformations for Multiple Instruction Retry. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1994, v:24, n:12, pp:1179-1198 [Journal]
  94. Aloke Gupta, Wen-mei W. Hwu
    An execution Profiler for Window-oriented Applications. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1993, v:23, n:5, pp:487-510 [Journal]
  95. Neal J. Alewine, Shyh-Kwei Chen, W. Kent Fuchs, Wen-mei W. Hwu
    Compiler-Assisted Multiple Instruction Rollback Recovery Using a Read Buffer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:9, pp:1096-1107 [Journal]
  96. Ronald D. Barnes, John W. Sias, Erik M. Nystrom, Sanjay J. Patel, Jose (Nacho) Navarro, Wen-mei W. Hwu
    Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:1, pp:18-33 [Journal]
  97. Pohua P. Chang, Daniel M. Lavery, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu
    The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:3, pp:353-370 [Journal]
  98. Pohua P. Chang, Nancy J. Warter, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu
    Three Architecutral Models for Compiler-Controlled Speculative Execution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:4, pp:481-494 [Journal]
  99. William Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu
    The Effect of Code Expanding Optimizations on Instruction Cache Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:9, pp:1045-1057 [Journal]
  100. Thomas M. Conte, Mary Ann Hirsch, Wen-mei W. Hwu
    Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:6, pp:714-720 [Journal]
  101. Wen-mei W. Hwu, Pohua P. Chang
    Efficient Instruction Sequencing with Inline Target Insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:12, pp:1537-1551 [Journal]
  102. Wen-mei W. Hwu, Thomas M. Conte
    The Susceptibility of Programs to Context Switching. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:9, pp:994-1003 [Journal]
  103. Wen-mei W. Hwu, Krishna V. Palem
    Guest Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:10, pp:1185-1187 [Journal]
  104. Wen-mei W. Hwu, Yale N. Patt
    Checkpoint Repair for High-Performance Out-of-Order Execution Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:12, pp:1496-1514 [Journal]
  105. Teresa L. Johnson, Daniel A. Connors, Matthew C. Merten, Wen-mei W. Hwu
    Run-Time Cache Bypassing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:12, pp:1338-1354 [Journal]
  106. Chung-Chi Jim Li, Shyh-Kwei Chen, W. Kent Fuchs, Wen-mei W. Hwu
    Compiler-Based Multiple Instruction Retry. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:1, pp:35-46 [Journal]
  107. Matthew C. Merten, Andrew R. Trick, Ronald D. Barnes, Erik M. Nystrom, Christopher N. George, John C. Gyllenhaal, Wen-mei W. Hwu
    An Architectural Framework for Runtime Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:6, pp:567-589 [Journal]
  108. Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker
    Sentinel Scheduling for VLIW and Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 1993, v:11, n:4, pp:376-408 [Journal]
  109. Wen-mei W. Hwu, Shane Ryoo, Sain-zee Ueng, John H. Kelm, Isaac Gelado, Sam S. Stone, Robert E. Kidd, Sara S. Baghsorkhi, Aqeel Mahesri, Stephanie C. Tsao, Nacho Navarro, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel
    Implicitly Parallel Programming Models for Thousand-Core Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:754-759 [Conf]
  110. Lauren Sarno, Wen-mei W. Hwu, Craig Lund, Markus Levy, James R. Larus, James Reinders, Gordon Cameron, Chris Lennard, Takashi Yoshimori
    Corezilla: Build and Tame the Multicore Beast? [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:632-633 [Conf]

  111. XMalloc: A Scalable Lock-free Dynamic Memory Allocator for Many-core Machines. [Citation Graph (, )][DBLP]


  112. CIGAR: Application Partitioning for a CPU/Coprocessor Architecture. [Citation Graph (, )][DBLP]


  113. Optimization of tele-immersion codes. [Citation Graph (, )][DBLP]


  114. High performance computation and interactive display of molecular orbitals on GPUs and multi-core CPUs. [Citation Graph (, )][DBLP]


  115. An asymmetric distributed shared memory model for heterogeneous parallel systems. [Citation Graph (, )][DBLP]


  116. Accelerating advanced mri reconstructions on gpus. [Citation Graph (, )][DBLP]


  117. GPU acceleration of cutoff pair potentials for molecular modeling applications. [Citation Graph (, )][DBLP]


  118. Program optimization space pruning for a multithreaded gpu. [Citation Graph (, )][DBLP]


  119. Efficient compilation of fine-grained SPMD-threaded programs for multicore CPUs. [Citation Graph (, )][DBLP]


  120. GPU clusters for high-performance computing. [Citation Graph (, )][DBLP]


  121. CUBA: an architecture for efficient CPU/co-processor data communication. [Citation Graph (, )][DBLP]


  122. High-performance CUDA kernel execution on FPGAs. [Citation Graph (, )][DBLP]


  123. Many-core parallel computing - Can compilers and tools do the heavy lifting? [Citation Graph (, )][DBLP]


  124. Long time-scale simulations of in vivo diffusion using GPU hardware. [Citation Graph (, )][DBLP]


  125. Accelerating MR Image Reconstruction on GPUS. [Citation Graph (, )][DBLP]


  126. Iteration Disambiguation for Parallelism Identification in Time-Sliced Applications. [Citation Graph (, )][DBLP]


  127. CUDA-Lite: Reducing GPU Programming Complexity. [Citation Graph (, )][DBLP]


  128. MCUDA: An Efficient Implementation of CUDA Kernels for Multi-core CPUs. [Citation Graph (, )][DBLP]


  129. Optimization principles and application performance evaluation of a multithreaded GPU using CUDA. [Citation Graph (, )][DBLP]


  130. An adaptive performance modeling tool for GPU architectures. [Citation Graph (, )][DBLP]


  131. Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor. [Citation Graph (, )][DBLP]


  132. FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs. [Citation Graph (, )][DBLP]


  133. Compute Unified Device Architecture Application Suitability. [Citation Graph (, )][DBLP]


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