Journals in DBLP
Dinos Moundanos , Jacob A. Abraham , Yatin Vasant Hoskote Abstraction Techniques for Validation Coverage Analysis and Test Generation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1998, v:47, n:1, pp:2-14 [Journal ] Fran Hanchek , Shantanu Dutt Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1998, v:47, n:1, pp:15-33 [Journal ] Elias Procópio Duarte Jr. , Takashi Nanya A Hierarachical Adaptive Distributed System-Level Diagnosis Algorithm. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1998, v:47, n:1, pp:34-45 [Journal ] Seungjae Han , Kang G. Shin A Primary-Backup Channel Approach to Dependable Real-Time Communication in Multihop Networks. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1998, v:47, n:1, pp:46-61 [Journal ] Michael Nicolaidis Fail-Safe Interfaces for VLSI: Theoretical Foundations and Implementation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1998, v:47, n:1, pp:62-77 [Journal ] Jean-Charles Fabre , Tanguy Pérennou A Metaobject Architecture for Fault-Tolerant Distributed Systems: The FRIENDS Approach. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1998, v:47, n:1, pp:78-95 [Journal ] Sachin Garg , Antonio Puliafito , Miklós Telek , Kishor S. Trivedi Analysis of Preventive Maintenance in Transactions Based Software Systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1998, v:47, n:1, pp:96-107 [Journal ] David T. Stott , Greg Ries , Mei-Chen Hsueh , Ravishankar K. Iyer Dependability Analysis of a High-Speed Network Using Software-Implemented Fault Injection and Simulated Fault Injection. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1998, v:47, n:1, pp:108-119 [Journal ] Mario Blaum , Jehoshua Bruck , Kurt Rubin , Wilfried Lenth A Coding Approach for Detection of Tampering in Write-Once Optical Disks. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1998, v:47, n:1, pp:120-125 [Journal ] Richard W. Linderman , Ralph L. R. Kohler , Mark H. Linderman A Dependable High Performance Wafer Scale Architecture for Embedded Signal Processing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1998, v:47, n:1, pp:125-128 [Journal ] Lama Nachman , Kewal K. Saluja , Shambhu J. Upadhyaya , Robert Reuse A Novel Approach to Random Pattern Testing of Sequential Circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1998, v:47, n:1, pp:129-134 [Journal ] Fong Pong , Michael C. Browne , Gunes Aybay , Andreas Nowatzyk , Michel Dubois Design Verification of the S3.mp Cache-Coherent Shared-Memory System. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1998, v:47, n:1, pp:135-140 [Journal ]