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Sotirios G. Ziavras: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jie Hu, Greg M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras
    Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:200-214 [Conf]
  2. Qian Wang, Sotirios G. Ziavras
    Network Embedding Techniques for a New Class of Feasible Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    Applied Informatics, 1999, pp:566-568 [Conf]
  3. Xizhen Xu, Sotirios G. Ziavras
    Iterative Methods for Solving Linear Systems of Equations on FPGA-Based Machines. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2003, pp:472-475 [Conf]
  4. Sotirios G. Ziavras
    Connection Machine Results for Pyramid Embedding Algorithms. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1992, pp:31-36 [Conf]
  5. Jie Hu, Shuai Wang, Sotirios G. Ziavras
    In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability. [Citation Graph (0, 0)][DBLP]
    DSN, 2006, pp:281-290 [Conf]
  6. Xizhen Xu, Sotirios G. Ziavras, Tae-Gyu Chang
    An FPGA-Based Parallel Accelerator for Matrix Multiplications in the Newton-Raphson Method. [Citation Graph (0, 0)][DBLP]
    EUC, 2005, pp:458-468 [Conf]
  7. Muhammad Z. Hasan, Sotirios G. Ziavras
    FPGA-Based Vector Processing for Solving Sparse Sets of Equations. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:331-332 [Conf]
  8. Xiaofang Wang, Sotirios G. Ziavras
    A Framework for Dynamic Resource Assignment and Scheduling on Reconfigurable Mixed-Mode On-Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:51-58 [Conf]
  9. Nikitas A. Alexandridis, Sotirios G. Ziavras, P. D. Tsanakas
    Architectural Adaptations for Hierarchical Image Processing/Transmission. [Citation Graph (0, 0)][DBLP]
    ICC, 1986, pp:424-428 [Conf]
  10. Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras
    Optimizing the Thermal Behavior of Subarrayed Data Caches. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:625-630 [Conf]
  11. Xizhen Xu, Sotirios G. Ziavras
    H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:671-676 [Conf]
  12. Sotirios G. Ziavras
    Techniques for Mapping Deterministic Algorithms onto Multi-Level Systems. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:226-233 [Conf]
  13. Dejiang Jin, Sotirios G. Ziavras
    Load Balancing on PC Clusters with the Super-Programming Model. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2003, pp:63-70 [Conf]
  14. Xiaofang Wang, Sotirios G. Ziavras
    Parallel Direct Solution of Linear Equations on FPGA-Based Machines. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:113- [Conf]
  15. Xiaofang Wang, Sotirios G. Ziavras
    A Configurable Multiprocessor and Dynamic Load Balancing for Parallel LU Factorization. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  16. Qian Wang, Sotirios G. Ziavras
    Powerful and Feasible Processor Interconnections With an Evaluation of Their Communications Capabilities. [Citation Graph (0, 0)][DBLP]
    ISPAN, 1999, pp:222-229 [Conf]
  17. Sotirios G. Ziavras
    Versatile Processor Design for Efficiency and High Performance. [Citation Graph (0, 0)][DBLP]
    ISPAN, 2000, pp:266-273 [Conf]
  18. Sotirios G. Ziavras
    Performance Analysis for an Important Class of Parallel-Processing Networks. [Citation Graph (0, 0)][DBLP]
    ISPAN, 1996, pp:500-506 [Conf]
  19. Xiaofang Wang, Sotirios G. Ziavras
    Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:386-391 [Conf]
  20. Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie Hu
    Vector Processing Support for FPGA-Oriented High Performance Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:447-448 [Conf]
  21. Shuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziavras
    Asymmetrically Banked Value-Aware Register Files. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:363-368 [Conf]
  22. Muhammad Z. Hasan, Sotirios G. Ziavras
    Runtime Partial Reconfiguration for Embedded Vector Processors. [Citation Graph (0, 0)][DBLP]
    ITNG, 2007, pp:983-988 [Conf]
  23. Hongyan Yang, Sotirios G. Ziavras, Jie Hu
    FPGA-based Vector Processing for Matrix Operations. [Citation Graph (0, 0)][DBLP]
    ITNG, 2007, pp:989-994 [Conf]
  24. Nagasimha G. Haravu, Sotirios G. Ziavras
    Processor Allocation for a Class of Hypercube-Like Supercomputers. [Citation Graph (0, 0)][DBLP]
    SC, 1992, pp:740-749 [Conf]
  25. Sotirios G. Ziavras, Qian Wang, Paraskevi Papathanasiou
    Viable Architectures for High-Performance Computing. [Citation Graph (0, 0)][DBLP]
    Comput. J., 2003, v:46, n:1, pp:36-54 [Journal]
  26. Xi Li, Sotirios G. Ziavras, Constantine N. Manikopoulos
    Parallel DSP algorithms on TurboNet: an experimental system with hybrid message-passing/shared-memory architecture. [Citation Graph (0, 0)][DBLP]
    Concurrency - Practice and Experience, 1996, v:8, n:5, pp:387-411 [Journal]
  27. Xi Li, Sotirios G. Ziavras, Constantine N. Manikopoulos
    Parallel generation of adaptive multiresolution structures for image processing. [Citation Graph (0, 0)][DBLP]
    Concurrency - Practice and Experience, 1997, v:9, n:4, pp:241-254 [Journal]
  28. Xiaofang Wang, Sotirios G. Ziavras
    Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines. [Citation Graph (0, 0)][DBLP]
    Concurrency and Computation: Practice and Experience, 2004, v:16, n:4, pp:319-343 [Journal]
  29. Sotirios G. Ziavras, Sanjay Krishnamurthy
    Evaluating the communications capabilities of the generalized hypercube interconnection network. [Citation Graph (0, 0)][DBLP]
    Concurrency - Practice and Experience, 1999, v:11, n:6, pp:281-300 [Journal]
  30. Sotirios G. Ziavras, Michalis A. Sideras
    Facilitating High-Performance Image Analysis on Reduced Hypercube (RH) Parallel Computers. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:4, pp:679-698 [Journal]
  31. Sotirios G. Ziavras
    Connected component labelling on the BLITZEN massively parallel processor. [Citation Graph (0, 0)][DBLP]
    Image Vision Comput., 1993, v:11, n:10, pp:665-668 [Journal]
  32. Sotirios G. Ziavras, Nikitas A. Alexandridis
    Improved algorithms for translation of pictures represented by leaf codes. [Citation Graph (0, 0)][DBLP]
    Image Vision Comput., 1988, v:6, n:1, pp:13-20 [Journal]
  33. Dejiang Jin, Sotirios G. Ziavras
    Modeling distributed data representation and its effect on parallel data accesses. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2005, v:65, n:10, pp:1281-1289 [Journal]
  34. Sotirios G. Ziavras
    On the Problem of Expanding Hypercube-Based Systems. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1992, v:16, n:1, pp:41-53 [Journal]
  35. Sotirios G. Ziavras, Peter Meer
    Adaptive Multiresolution Structures for Image Processing on Parallel Computers. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1994, v:23, n:3, pp:475-483 [Journal]
  36. Satchidanand G. Haridas, Sotirios G. Ziavras
    FPGA implementation of a Cholesky algorithm for a shared-memory multiprocessor architecture. [Citation Graph (0, 0)][DBLP]
    Parallel Algorithms Appl., 2004, v:19, n:4, pp:211-226 [Journal]
  37. Sotirios G. Ziavras, Arup Mukherjee
    Data Broadcasting and Reduction, Prefix Computation, and Sorting on Reduces Hypercube Parallel Computer. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1996, v:22, n:4, pp:595-606 [Journal]
  38. Sotirios G. Ziavras
    Scalable Multifolded Hypercubes for versatile Parallel Computers. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1995, v:5, n:, pp:241-250 [Journal]
  39. Dejiang Jin, Sotirios G. Ziavras
    A Super-Programming Approach for Mining Association Rules in Parallel on PC Clusters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2004, v:15, n:9, pp:783-794 [Journal]
  40. Sotirios G. Ziavras
    Efficient Mapping Algorithms for a Class of Hierarchical Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:11, pp:1230-1245 [Journal]
  41. Sotirios G. Ziavras
    RH: A Versatile Family of Reduced Hypercube Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:11, pp:1210-1220 [Journal]
  42. Sotirios G. Ziavras
    Processor design based on dataflow concurrency. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2003, v:27, n:4, pp:199-220 [Journal]
  43. Segreen Ingersoll, Sotirios G. Ziavras
    Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs). [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2002, v:26, n:6, pp:263-280 [Journal]
  44. Shuai Wang, Jie Hu, Sotirios G. Ziavras
    On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:14-20 [Conf]
  45. Sotirios G. Ziavras, Haim Grebel, Anthony T. Chronopoulos, Florent Marcelli
    A new-generation parallel computer and its performance evaluation. [Citation Graph (0, 0)][DBLP]
    Future Generation Comp. Syst., 2000, v:17, n:3, pp:315-333 [Journal]
  46. Sotirios G. Ziavras, Alexandros V. Gerbessiotis, Rohan Bafna
    Coprocessor design to support MPI primitives in configurable multiprocessors. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:235-252 [Journal]

  47. Exploiting narrow-width values for thermal-aware register file designs. [Citation Graph (, )][DBLP]


  48. Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors. [Citation Graph (, )][DBLP]


  49. Identity Inference as a Privacy Risk in Computer-Mediated Communication. [Citation Graph (, )][DBLP]


  50. System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors. [Citation Graph (, )][DBLP]


  51. Preventing Unwanted Social Inferences with Classification Tree Analysis. [Citation Graph (, )][DBLP]


  52. BTB Access Filtering: A Low Energy and High Performance Design. [Citation Graph (, )][DBLP]


  53. A Study of Data Exchange Protocols for the Grid Computing Environment. [Citation Graph (, )][DBLP]


  54. Measuring Network Parameters with Hardware Support. [Citation Graph (, )][DBLP]


  55. Novel FPGA-Based Signature Matching for Deep Packet Inspection. [Citation Graph (, )][DBLP]


  56. Designing for different levels of social inference risk. [Citation Graph (, )][DBLP]


  57. Social Inference Risk Modeling in Mobile and Social Applications. [Citation Graph (, )][DBLP]


  58. Efficient hardware support for pattern matching in network intrusion detection. [Citation Graph (, )][DBLP]


  59. High-performance emulation of hierarchical structures on hypercube supercomputers. [Citation Graph (, )][DBLP]


  60. Pyramid mappings onto hypercubes for computer vision: Connection machine comparative study. [Citation Graph (, )][DBLP]


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