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Conferences in DBLP

IEEE International Conference on Field-Programmable Technology (FPT) (fpt)
2005 (conf/fpt/2005)

  1. Marcio Juliato, Guido Araujo, Julio López, Ricardo Dahab
    A custom instruction approach for hardware and software implementations of finite field arithmetic over F263 using Gaussian normal bases. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:5-12 [Conf]
  2. Ciaran McIvor, Máire McLoone, John V. McCanny
    High-Radix Systolic Modular Multiplication on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:13-18 [Conf]
  3. Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon
    Pipelining Saturated Accumulation. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:19-26 [Conf]
  4. Jérémie Detrey, Florent de Dinechin
    A Parameterized Floating-Point Exponential Function for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:27-34 [Conf]
  5. Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich
    The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:37-42 [Conf]
  6. Markus Koester, Mario Porrmann, Heiko Kalte
    Task Placement for Heterogeneous Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:43-50 [Conf]
  7. Xiaofang Wang, Sotirios G. Ziavras
    A Framework for Dynamic Resource Assignment and Scheduling on Reconfigurable Mixed-Mode On-Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:51-58 [Conf]
  8. David B. Thomas, Wayne Luk
    High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:61-68 [Conf]
  9. Shin'ichi Wakabayashi, Kenji Kikuchi
    Solving the Minimum Dominating Set Problem with Instance-Specific Hardware on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:69-76 [Conf]
  10. M. P. T. Juvonen, José Gabriel F. Coutinho, J. L. Wang, B. L. Lo, Wayne Luk, Oskar Mencer, G. Z. Yang
    Custom Hardware Architectures for Posture Analysis. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:77-84 [Conf]
  11. Almudena Lindoso, Luis Entrena, Celia López-Ongil, Judith Liu-Jimenez
    Correlation-Based Fingerprint Matching Using FPGAs. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:87-94 [Conf]
  12. Kofi Appiah, Andrew Hunter
    A Single-Chip FPGA Implementation of Real-Time Adaptive Background Model. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:95-102 [Conf]
  13. Erdem Motuk, Roger Woods, Stefan Bilbao
    FPGA-Based Hardware for Physical Modelling Sound Synthesis by Finite Difference Schemes. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:103-110 [Conf]
  14. Ben Cope, Peter Y. K. Cheung, Wayne Luk, Sarah Witt
    Have GPUs Made FPGAs Redundant in the Field of Video Processing? [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:111-118 [Conf]
  15. Jeffrey M. Arnold
    S5: The Architecture and Development Flow of a Software Configurable Processor. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:121-128 [Conf]
  16. Vasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano
    RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:129-136 [Conf]
  17. Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
    Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:137-144 [Conf]
  18. Máire McLoone, Ciaran McIvor, Aidan Savage
    High-Speed Hardware Architectures of the Whirlpool Hash Function. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:147-162 [Conf]
  19. Amir Sheikh Zeineddini, Kris Gaj
    Secure Partial Reconfiguration of FPGAs. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:155-162 [Conf]
  20. Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima
    An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:163-170 [Conf]
  21. C. T. Chow, L. S. M. Tsui, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
    Dynamic Voltage Scaling for Commercial FPGAs. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:173-180 [Conf]
  22. Rajarshee P. Bharadwaj, Rajan Konar, Dinesh Bhatia, Poras T. Balsara
    FPGA Architecture for Standby Power Management. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:181-188 [Conf]
  23. Anthony J. Yu, Guy G. Lemieux
    FPGA Defect Tolerance: Impact of Granularity. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:189-196 [Conf]
  24. Irwin Kennedy
    A Dynamically Reconfigured UMTS Multi-Channel Complex Code Matched Filter. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:199-206 [Conf]
  25. Esam El-Araby, Mohamed Taher, Tarek A. El-Ghazawi, Jacqueline Le Moigne
    Prototyping Automatic Cloud Cover Assessment (ACCA) Algorithm for Remote Sensing On-Board Processing on a Reconfigurable Computer. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:207-214 [Conf]
  26. G. L. Zhang, Philip Heng Wai Leong, Chun Hok Ho, Kuen Hung Tsoi, C. C. C. Cheung, Dong-U Lee, Ray C. C. Cheung, Wayne Luk
    Reconfigurable Acceleration for Monte Carlo Based Financial Simulation. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:215-222 [Conf]
  27. Akshay Sharma, Scott Hauck
    Accelerating FPGA Routing Using Architecture-Adaptive A* Techniques. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:225-232 [Conf]
  28. Nastaran Baradaran, Pedro C. Diniz
    Compiler-Directed Design Space Exploration for Caching and Prefetching Data in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:233-240 [Conf]
  29. Bradley R. Quinton, Steven J. E. Wilton
    Post-Silicon Debug Using Programmable Logic Cores. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:241-248 [Conf]
  30. Oswaldo Cadenas, Graham M. Megson, Daniel Jones
    FPGA Organization for the Fast Path-Based Neural Branch Predictor. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:251-258 [Conf]
  31. Cesar Torres-Huitzil, Bernard Girau
    FPGA Implementation of an Excitatory and Inhibitory Connectionist Model for Motion Perception. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:259-266 [Conf]
  32. Yoshiki Yamaguchi, Tsutomu Maruyama, Ryuzo Azuma, Akihiko Konagaya
    Spatiotemporal Simulation of a Single Living Cell. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:267-274 [Conf]
  33. Yi Lu, Neil W. Bergmann
    Dynamic Loading of Peripherals on Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:279-280 [Conf]
  34. Timothy F. Oliver, Douglas L. Maskell
    An FPGA Model for Developing Dynamic Circuit Computing. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:281-282 [Conf]
  35. Andrew Bainbridge-Smith, Su-Hyun Park
    ADH: An Aspect Described Hardware Programming Language. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:283-284 [Conf]
  36. Wolfgang Klingauf, Robert Günzel
    From TLM to FPGA: Rapid Prototyping with SystemC and Transaction Level Modeling. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:285-286 [Conf]
  37. Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi
    Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse Lasers. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:287-288 [Conf]
  38. Ivan Gonzalez, Francisco J. Gomez-Arribas, Sergio López-Buedo
    Hardware-Accelerated SSH on Self-Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:289-290 [Conf]
  39. Arvind Sudarsanam, Aravind Dasu
    A Fast and Efficient FPGA-Based Implementation for Solving a System of Linear Interval Equations. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:291-292 [Conf]
  40. Sebastian Lange, Martin Middendorf
    Heuristics for Context-Caches in 2-Level Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:293-294 [Conf]
  41. John Harkins, Tarek A. El-Ghazawi, Esam El-Araby, Miaoqing Huang
    Performance of Sorting Algorithms on the SRC 6 Reconfigurable Computer. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:295-296 [Conf]
  42. Minoru Watanabe, Fuminori Kobayashi
    A Zero-Overhead Dynamic Optically Reconfigurable Gate Array. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:297-298 [Conf]
  43. Joshua Fender, Jonathan Rose, David R. Galloway
    The Transmogrifier-4: An FPGA-Based Hardware Development System with Multi-Gigabyte Memory Capacity and High Host and Memory Bandwidth. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:301-302 [Conf]
  44. Alberto Dassatti, Guido Masera, Mario Nicola, Andrea Concil, Angelo Poloni
    High Performance Channel Model Hardware Emulator for 802.11n. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:303-304 [Conf]
  45. Feng Lin, Haili Wang, Jinian Bian
    HW/SW Interface Synthesis Based on Avalon Bus Specification for Nios-Oriented SoC Design. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:305-306 [Conf]
  46. Ali Valizadeh, Morteza Saheb Zamani, Babak Sadeghian, Farhad Mehdipour
    A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:307-308 [Conf]
  47. Chang Shu, Kris Gaj, Tarek A. El-Ghazawi
    Low Latency Elliptic Curve Cryptography Accelerators for NIST Curves Over Binary Fields. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:309-310 [Conf]
  48. Esam El-Araby, Tarek A. El-Ghazawi, Kris Gaj
    A System-Level Design Methodology for Reconfigurable Computing Applications. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:311-312 [Conf]
  49. Mihail Petrov, Manfred Glesner
    Optimal FFT Architecture Selection for OFDM Receivers on FPGA. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:313-314 [Conf]
  50. Patrick Dickinson, Kofi Appiah, Andrew Hunter, Stephen Ormston
    An FPGA-Based Infant Monitoring System. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:315-316 [Conf]
  51. Andrew Kinane, Alan Casey, Valentin Muresan, Noel E. O'Connor
    FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:317-318 [Conf]
  52. S. Fischaber, R. Hasson, John McAllister, Roger Woods
    FPGA Core Network Implementation and Optimization: A Case Study. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:319-320 [Conf]
  53. Mihail Petrov, Manfred Glesner
    A State-Serial Viterbi Decoder Architecture for Digital Radio on FPGA. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:323-324 [Conf]
  54. Gerd Van den Branden, Abdellah Touhafi, Erik F. Dirkx
    A Design Methodology to Generate Dynamically Self-Reconfigurable SoCs for Virtex-II Pro FPGAs. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:325-326 [Conf]
  55. Ocean Y. H. Cheung, Philip Heng Wai Leong, Eric K. C. Tsang, Bertram Emil Shi
    Implementation of Gabor-Type Filters on Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:327-328 [Conf]
  56. P. Potipantong, Theerayod Wiangtong, Phaophak Sirisuk, Apisak Worapishet
    A Scaleable FFT/IFFT Kernel for Communication Systems Using Codesign Approach. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:329-330 [Conf]
  57. Laurence A. Hey, Peter Y. K. Cheung, Michael Gellman
    FPGA Based Router for Cognitive Packet Networks. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:331-332 [Conf]
  58. Andreas Fidjeland, Wayne Luk
    An Overview of High-Level Synthesis of Multiprocessors for Logic Programming. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:333-334 [Conf]
  59. Milind M. Parelkar, Kris Gaj
    Implementation of EAX Mode of Operation for FPGA Bitstream Encryption and Authentication. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:335-336 [Conf]
  60. Siobhán Launders, Wesley Cooper, Brian Foley
    Net Power Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:337-338 [Conf]
  61. Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano
    The Design of Scalable Stochastic Biochemical Simulator on FPGA. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:339-340 [Conf]
  62. Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow
    Designing an FPGA SoC Using a Standardized IP Block Interface. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:341-342 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002