Conferences in DBLP
Gerhard Knoblinger , James Tschanz , Marcal Pol SUB-45nm Technology and Design Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Gerhard Knoblinger Multi-Gate MOSFET Design. [Citation Graph (0, 0)][DBLP ] Conf ] James Tschanz SUB 45nm Low Power Design Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Marcal Pol Self-Adaptive Systems to Drive out the Nano-Scale Devil. [Citation Graph (0, 0)][DBLP ] Conf ] Nagesh Nagapalli DFT and Test: Ensuring Product Quality. [Citation Graph (0, 0)][DBLP ] Conf ] Srikanth Venkataraman DFM, DFY, Debug and Diagnosis: The Loop to Ensure Yield. [Citation Graph (0, 0)][DBLP ] Conf ] Srikanth Venkataraman , Nagesh Nagapalli , Lech Jozwiak Quality Driven Manufacturing and SOC Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Lech Józwiak Quality-Driven Architecture Synthesis and Power Aware Design of Embedded SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Resve Saleh , Pallab K. Chatterjee , Ivan Pesic , Robbert Dobkins , Mike Smayling , Joseph Sawicki DFM-EDA's Salvation or its Excuse for Being out of Touch with Engineering? [Citation Graph (0, 0)][DBLP ] Conf ] Jeong-Taek Kong Tipping Point for New Design Technologies: DFM, Low Power and ESL. [Citation Graph (0, 0)][DBLP ] Conf ] Duane S. Boning , Karthik Balakrishnan , Hong Cai , Nigel Drego , Ali Farahanchi , Karen Gettings , Daihyun Lim , Ajay Somani , Hayden Taylor , Daniel Truque , Xiaolin Xie Variation. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Sato , Takumi Uezono , Shiho Hagiwara , Kenichi Okada , Shuhei Amakawa , Noriaki Nakayama , Kazuya Masu A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. [Citation Graph (0, 0)][DBLP ] Conf ] Rajani Kuchipudi , Hamid Mahmoodi Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Rouwaida Kanj , Rajiv V. Joshi , Jayakumaran Sivagnaname , Jente B. Kuang , Dhruva Acharyya , Tuyet Nguyen , Chandler McDowell , Sani R. Nassif Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Rakesh Vattikonda , Yansheng Luo , Alex Gyure , Xiaoning Qi , Sam C. Lo , Mahmoud Shahram , Yu Cao , Kishore Singhal , Dino Toffolon A New Simulation Method for NBTI Analysis in SPICE Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Xiangning Yang , Kewal K. Saluja Combating NBTI Degradation via Gate Sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Benoit Dubois , Jean-Baptiste Kammerer , Luc Hebrard , Francis Braun Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability. [Citation Graph (0, 0)][DBLP ] Conf ] Aram Shin , Sang Jun Hwang , Seung Woo Yu , Man Young Sung A New Organic Thin-Film Transistor Based Current-Driving Pixel Circuit for Active-Matrix Organic Light-Emitting Displays. [Citation Graph (0, 0)][DBLP ] Conf ] Mosin Mondal , Andrew J. Ricketts , Sami Kirolos , Tamer Ragheb , Greg M. Link , Narayanan Vijaykrishnan , Yehia Massoud Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers. [Citation Graph (0, 0)][DBLP ] Conf ] Sherif A. Tawfik , Volkan Kursun Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew. [Citation Graph (0, 0)][DBLP ] Conf ] Weihuang Wang , Gwan Choi Speculative Energy Scheduling for LDPC Decoding. [Citation Graph (0, 0)][DBLP ] Conf ] Kanak Agarwal , Kevin J. Nowka Dynamic Power Management by Combination of Dual Static Supply Voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Hazucha , Fabrice Paillet , Sung Tae Moon , David J. Rennie , Gerhard Schrom , Donald S. Gardner , Kenneth Ikeda , Gell Gellman , Tanay Karnik Low Voltage Buffered Bandgap Reference. [Citation Graph (0, 0)][DBLP ] Conf ] Pengfei Li , Rizwan Bashirullah A DLL Based Multiphase Hysteretic DC-DC Converter. [Citation Graph (0, 0)][DBLP ] Conf ] Hong Li , Cheng-Kok Koh , Venkataramanan Balakrishnan , Yiran Chen Statistical Timing Analysis Considering Spatial Correlations. [Citation Graph (0, 0)][DBLP ] Conf ] Liang Rong , E. Martin I. Gustafsson , Ana Rusu , Mohammed Ismail Systematic Design of a Flash ADC for UWB Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas W. Williams EDA to the Rescue of the Silicon Roadmap. [Citation Graph (0, 0)][DBLP ] Conf ] Arthur Nieuwoudt , Yehia Massoud Assessing the Implications of Process Variations on Future Carbon Nanotube Bundle Interconnect Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Tamer Cakici , Kee-Jong Kim , Kaushik Roy FinFET Based SRAM Design for Low Standby Power Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Asha Balijepalli , Joseph Ervin , Yu Cao , Trevor Thornton Compact Modeling of a PD SOI MESFET for Wide Temperature Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Hong Luo , Yu Wang , Ku He , Rong Luo , Huazhong Yang , Yuan Xie Modeling of PMOS NBTI Effect Considering Temperature Variation. [Citation Graph (0, 0)][DBLP ] Conf ] Jie Deng , Keunwoo Kim , Ching-Te Chuang , H.-S. Philip Wong Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed Youssef , Tor Myklebust , Mohab Anis , Mohamed I. Elmasry A Low-Power Multi-Pin Maze Routing Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Pei-Yu Huang , Huan-Yu Chou , Yu-Min Lee An Aggregation-Based Algebraic Multigrid Method for Power Grid Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Gustavo R. Wilke , Rajeev Murgai Design and Analysis of "Tree+Local Meshes" Clock Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Zhanyuan Jiang , Shiyan Hu , Jiang Hu , Weiping Shi An Efficient Algorithm for RLC Buffer Insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Nahmsuk Oh , Alireza Kasnavi , Peivand F. Tehrani Fast Crosstalk Repair by Quick Timing Change Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Minh Quang Do , Mindaugas Drazdziulis , Per Larsson-Edefors , Lars Bengtsson Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Amin Khajeh Djahromi , Ahmed M. Eltawil , Fadi J. Kurdahi , Rouwaida Kanj Cross Layer Error Exploitation for Aggressive Voltage Scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Hwisung Jung , Massoud Pedram A Unified Framework for System-Level Design: Modeling and Performance Optimization of Scalable Networking Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yongpan Liu , Huazhong Yang , Robert P. Dick , Hui Wang , Li Shang Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Foad Dabiri , Roozbeh Jafari , Ani Nahapetian , Majid Sarrafzadeh A Unified Optimal Voltage Selection Methodology for Low-Power Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Charbel J. Akl , Magdy A. Bayoumi Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Bi Yuan , Yi Zhang , Lili He A 8b 10Ms/s Low Power Pipelined A/D Converter. [Citation Graph (0, 0)][DBLP ] Conf ] Yamei Li , Lili He First-Order Continuous-Time Sigma-Delta Modulator. [Citation Graph (0, 0)][DBLP ] Conf ] Yokesh Kumar , Prosenjit Gupta Reducing EPL Alignment Errors for Large VLSI Layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiyu Liu , Volkan Kursun Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Taeyong Je , Yungseon Eo Efficient Signal Integrity Verification of Multi-Coupled Transmission Lines with Asynchronously Switching Non-Linear Drivers. [Citation Graph (0, 0)][DBLP ] Conf ] Ling Zhang , Hongyu Chen , Bo Yao , Kevin Hamilton , Chung-Kuan Cheng Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals. [Citation Graph (0, 0)][DBLP ] Conf ] Bao Liu Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Xudong Niu , Yan Song , Bo Li , Wei Bian , Yadong Tao , Feng Liu , Jinhua Hu , Yu Chen , Frank He Tests on Symmetry and Continuity between BSIM4 and BSIM5. [Citation Graph (0, 0)][DBLP ] Conf ] Naiyong Jin , Taoyong Ni Interface Specification Assurance Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Zhenyu (Jerry) Qi , Matthew M. Ziegler , Stephen V. Kosonocky , Jan M. Rabaey , Mircea R. Stan Multi-Dimensional Circuit and Micro-Architecture Level Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Nigel Drego , Anantha Chandrakasan , Duane S. Boning A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Rishi Bhooshan Novel and Efficient IR-Drop Models for Designing Power Distribution Network for Sub-100nm Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Alfred L. Crouch , Phil Burlison , Dennis J. Ciplickas Processing High Volume Scan Test Results for Yield Learning. [Citation Graph (0, 0)][DBLP ] Conf ] Weixiang Shen , Yici Cai , Xianlong Hong , Jiang Hu , Bing Lu Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] David Rennie , Manoj Sachdev Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Daniela De Venuto , Bruno Riccò Inductive Fault Analysis for Test and Diagnosis of DNA Sensor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Ndai , Shih-Lien Lu , Dinesh Somasekhar , Kaushik Roy Fine-Grained Redundancy in Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Abby A. Ilumoka , Hong Lang Tan MEMS Failure Probability Prediction and Quality Enhancement Using Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] V. Mahalingam , N. Ranganathan Variation Aware Timing Based Placement Using Fuzzy Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Amol Mupid , Madhu Mutyam , Narayanan Vijaykrishnan , Yuan Xie , Mary Jane Irwin Variation Analysis of CAM Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Qi Lin , Mei Ma , Tony Vo , Jenny Fan , Xin Wu , Richard Li , Xiao-Yu Li Design-for-Manufacture for Multi Gate Oxide CMOS Process. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Min Kuo , Cheng-Hung Lin , Chun-Yao Wang , Shih-Chieh Chang , Pei-Hsin Ho Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Yici Cai , Bin Liu , Jin Shi , Qiang Zhou , Xianlong Hong Power Delivery Aware Floorplanning for Voltage Island Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Boyuan Yan , Pu Liu , Sheldon X.-D. Tan , Bruce McGaughy Passive Modeling of Interconnects by Waveform Shaping. [Citation Graph (0, 0)][DBLP ] Conf ] Kaijian Shi , Zhian Lin , Yi-Min Jiang A Power Network Synthesis Method for Industrial Power Gating Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan Cai , Sudhakar M. Reddy , Bashir M. Al-Hashimi Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint. [Citation Graph (0, 0)][DBLP ] Conf ] Yuji Kunitake , Akihiro Chiyonobu , Koichiro Tanaka , Toshinori Sato Challenges in Evaluations for a Typical-Case Design Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Hamid R. Zarandi , Seyed Ghassem Miremadi , Dhiraj K. Pradhan , Jimson Mathew SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaofang Wang , Sotirios G. Ziavras Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Gautam Kumar Singh , Santosh Kumar Panigrahi A High Frequency PWM Controller in HV Bi-CMOS Process Considering SOI Self-Heating. [Citation Graph (0, 0)][DBLP ] Conf ] Joon-Sung Yang , Anand Rajaram , Ninghy Shi , Jian Chen , David Z. Pan Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Chaoming Zhang , Ranjit Gharpurey , Jacob A. Abraham Built-In Test of RF Mixers Using RF Amplitude Detectors. [Citation Graph (0, 0)][DBLP ] Conf ] Michael N. Skoufis , Haibo Wang , Themistoklis Haniotakis , Spyros Tragoudas Glitch Control with Dynamic Receiver Threshold Adjustment. [Citation Graph (0, 0)][DBLP ] Conf ] Yong Sin Kim , Sung-Mo Kang Programmable High Speed Multi-Level Simultaneous Bidirectional I/O. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Kumar Goparaju , Spyros Tragoudas A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations. [Citation Graph (0, 0)][DBLP ] Conf ] Kumar Yelamarthi , Chien-In Henry Chen Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Mehboob Alam , Arthur Nieuwoudt , Yehia Massoud Wavelet-Based Passivity Preserving Model Order Reduction for Wideband Interconnect Characterization. [Citation Graph (0, 0)][DBLP ] Conf ] Taraneh Taghavi , Ani Nahapetian , Majid Sarrafzadeh System Level Estimation of Interconnect Length in the Presence of IP Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Rasit Onur Topaloglu Energy-Minimization Model for Fill Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Santosh Shah , Arani Sinha , Li Song , Narain D. Arora On-Chip Inductance in X Architecture Enabled Design. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok Narasimhan , Ramalingam Sridhar Impact of Variability on Clock Skew in H-tree Clock Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Rasit Onur Topaloglu A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances. [Citation Graph (0, 0)][DBLP ] Conf ] Jeong-Yeol Kim , Ho-Soon Shin , Jong-Bae Lee , Moon-Hyun Yoo , Jeong-Taek Kong SilcVerify: An Efficient Substrate Coupling Noise Simulation Tool for High-Speed & Nano-Scaled Memory Design. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Zou , Daniel Mueller , Helmut E. Graeb , Ulf Schlichtmann Pareto-Front Computation and Automatic Sizing of CPPLLs. [Citation Graph (0, 0)][DBLP ] Conf ] Kai-Hui Chang , David A. Papa , Igor L. Markov , Valeria Bertacco InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization. [Citation Graph (0, 0)][DBLP ] Conf ] Joonsung Park , Hongjoong Shin , Jacob A. Abraham Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Laknaur , Rui Xiao , Sai Raghuram Durbha , Haibo Wang Design of a Window Comparator with Adaptive Error Threshold for Online Testing Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunsik Kim , Yungseon Eo High-Frequency-Measurement-Based Frequency-Variant Transmission Line Characterization and Circuit Modeling for Accurate Signal Integrity Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Guo Yu , Peng Li , Wei Dong Achieving Low-Cost Linearity Test and Diagnosis of Sigma Delta ADCs via Frequency-Domain Nonlinear Analysis and Macromodeling. [Citation Graph (0, 0)][DBLP ] Conf ] Daniela De Venuto , Leonardo Reyneri Fully Digital Optimized Testing and Calibration Technique for Sigma Delta ADC's. [Citation Graph (0, 0)][DBLP ] Conf ] Youngsoo Shin , Hyung-Ock Kim Cell-Based Semicustom Design of Zigzag Power Gating Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Byunghee Choi , Youngsoo Shin Lookup Table-Based Adaptive Body Biasing of Multiple Macros. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinori Sato , Yuji Kunitake A Simple Flip-Flop Circuit for Typical-Case Designs for DFM. [Citation Graph (0, 0)][DBLP ] Conf ] Jaydeep P. Kulkarni , Kaushik Roy A High Performance, Scalable Multiplexed Keeper Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Sherief Reda , Puneet Sharma On-Line Adjustable Buffering for Runtime Power Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Duranton Programmable Engines for Embedded Systems: The New Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Derbey Soft-Errors Phenomenon Impacts on Design for Reliability Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph Sawicki Forging Tighter Connections Between Design and Manufacturing in the Nanometer Age. [Citation Graph (0, 0)][DBLP ] Conf ] Dongkeun Oh , Charlie Chung Ping Chen , Yu Hen Hu 3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function Method. [Citation Graph (0, 0)][DBLP ] Conf ] Eunseok Song , Heeseok Lee , Jungtae Lee , Woojin Jin , Kiwon Choi , Sa-Yoon Kang Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design. [Citation Graph (0, 0)][DBLP ] Conf ] Syed M. Alam , Robert E. Jones , Shahid Rauf , Ritwik Chatterjee Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Juan Pablo Martinez Brito , Hamilton Klimach , Sergio Bampi A Design Methodology for Matching Improvement in Bandgap References. [Citation Graph (0, 0)][DBLP ] Conf ] David Zaretsky , Gaurav Mittal , Robert P. Dick , Prith Banerjee Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng-Tao Hsieh , Jian-Cheng Lin , Shih-Chieh Chang Efficient Transition-Mode Boolean Characteristic Function with Its Application to Maximum Instantaneous Current Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitri Kagaris , Themistoklis Haniotakis Transistor-Level Synthesis for Low-Power Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Boule , Jean-Samuel Chenard , Zeljko Zilic Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Jae-sun Seo , Prashant Singh , Dennis Sylvester , David Blaauw Self-Time Regenerators for High-Speed and Low-Power Interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Hong Li , Jitesh Jain , Venkataramanan Balakrishnan , Cheng-Kok Koh Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization. [Citation Graph (0, 0)][DBLP ] Conf ] Ning Mi , Boyuan Yan , Sheldon X.-D. Tan , Jeffrey Fan , Hao Yu General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Mini Nanua , David Blaauw Investigating Crosstalk in Sub-Threshold Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Smruti R. Sarangi , Brian Greskamp , Josep Torrellas A Model for Timing Errors in Processors with Parameter Variation. [Citation Graph (0, 0)][DBLP ] Conf ] Mosin Mondal , Kartik Mohanram , Yehia Massoud Parameter-Variation-Aware Analysis for Noise Robustness. [Citation Graph (0, 0)][DBLP ] Conf ] Kenichi Shinkai , Masanori Hashimoto , Takao Onoye Future Prediction of Self-Heating in Short Intra-Block Wires. [Citation Graph (0, 0)][DBLP ] Conf ] Javid Jaffari , Mohab Anis Thermal-Aware Placement for FPGAs Using Electrostatic Charge Model. [Citation Graph (0, 0)][DBLP ] Conf ] Jacques Benkoski , Michelle Clancy , Shankar Krishnamoorthy , David Holt , Ravi Subramanian , Clive Bittlestone , Tsuyoshi Yamamoto , Andrew Kanhg Do Digital Design and Variability Mix like Oil and Water? [Citation Graph (0, 0)][DBLP ] Conf ] Ayhan A. Mutlu , Kelvin J. Le , Mustafa Celik , Dar-sun Tsien , Garry Shyu , Long-Ching Yeh An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Amith Singhee , Rob A. Rutenbar From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Aitken Defect or Variation? Characterizing Standard Cell Behavior at 90nm and below. [Citation Graph (0, 0)][DBLP ] Conf ] Choongyeun Cho , Daeik Kim , Jonghae Kim , Jean-Olivier Plouchart , Daihyun Lim , Sangyeun Cho , Robert Trzcinski A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Uthman Alsaiari , Resve Saleh Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeshwary Tayade , Savithri Sundereswaran , Jacob Abraham Small-Delay Defect Detection in the Presence of Process Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Rajsekhar Adapa , Edward Flanigan , Spyros Tragoudas , Michael Laisne , Hailong Cui , Tsvetomir Petrov Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Alodeep Sanyal , Kunal P. Ganeshpure , Sandip Kundu On Accelerating Soft-Error Detection by Targeted Pattern Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Edward Flanigan , Spyros Tragoudas Enhanced Identification of Strong Robustly Testable Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Zhuo Feng , Guo Yu , Peng Li Reducing the Complexity of VLSI Performance Variation Modeling Via Parameter Dimension Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Ning Lu , Judy H. McCullen Enablement of Variation-Aware Timing: Treatment of Parasitic Resistance and Capacitance. [Citation Graph (0, 0)][DBLP ] Conf ] Yang Liu , Tong Zhang , Jiang Hu Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders. [Citation Graph (0, 0)][DBLP ] Conf ] Sivasubramaniam Krishnamurthy , Somnath Paul , Swarup Bhunia Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Dasdan , Jinfeng Liu , Sridhar Tirumala , Kayhan Küçükçakar Designing and Validating Process-Variation-Aware Cell Libraries. [Citation Graph (0, 0)][DBLP ] Conf ] Jianliang Li , Qiliang Yan , Lawrence S. Melvin III Transferring Optical Proximity Correction (OPC) Effect into Optical Mode. [Citation Graph (0, 0)][DBLP ] Conf ] Tetsuya Iizuka , Makoto Ikeda , Kunihiro Asada OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Ye Chen , Zheng Shi , Xiaolang Yan An Automated and Fast OPC Algorithm for OPC-Aware Layout Design. [Citation Graph (0, 0)][DBLP ] Conf ] Yufu Zhang , Zheng Shi A New Method of Implementing Hierarchical OPC. [Citation Graph (0, 0)][DBLP ] Conf ] Subarna Sinha , Qing Su , Linni Wen , Frank Lee , Charles Chiang , Yi-Kan Cheng , Jin-Lien Lin , Yu-Chyi Harn A New Flexible Algorithm for Random Yield Improvement. [Citation Graph (0, 0)][DBLP ] Conf ] Arthur Nieuwoudt , Tamer Ragheb , Hamid Nejati , Yehia Massoud Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process Variations. [Citation Graph (0, 0)][DBLP ] Conf ] S. Ramsundar , Ahmad A. Al-Yamani , Dhiraj K. Pradhan Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Shubhankar Basu , Priyanka Thakore , Ranga Vemuri Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin W. McCullen Redundant Via Insertion in Restricted Topology Layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Chen Li 0004 , Cheng-Kok Koh Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Hongjie Bai , Sheqin Dong , Xianlong Hong Congestion Driven Buffer Planning for X-Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Zhuo Li , Charles J. Alpert , Stephen T. Quay , Sachin S. Sapatnekar , Weiping Shi Probabilistic Congestion Prediction with Partial Blockages. [Citation Graph (0, 0)][DBLP ] Conf ] Hua Xiang , Liang Deng , Li-Da Huang , Martin D. F. Wong OPC-Friendly Bus Driven Floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Hailin Jiang , Malgorzata Marek-Sadowska Power-Gating Aware Floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Frederic Worm , Patrick Thiran , Paolo Ienne Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen Bhojwani , Rabi N. Mahapatra An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Mosin Mondal , Tamer Ragheb , Xiang Wu , Adnan Aziz , Yehia Massoud Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Ting-Chun Huang , Ümit Y. Ogras , Radu Marculescu Virtual Channels Planning for Networks-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Vyas Krishnan , Srinivas Katkoori A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Natasa Miskov-Zivanov , Diana Marculescu MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Liang Wang , Suge Yue , Yuanfu Zhao , Long Fan An SEU-Tolerant Programmable Frequency Divider. [Citation Graph (0, 0)][DBLP ] Conf ] Roystein Oliveira , Aditya Jagirdar , Tapan J. Chakraborty A TMR Scheme for SEU Mitigation in Scan Flip-Flops. [Citation Graph (0, 0)][DBLP ] Conf ] K. Ramakrishnan , R. Rajaraman , S. Suresh , Narayanan Vijaykrishnan , Yuan Xie , Mary Jane Irwin Variation Impact on SER of Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Christian J. Hescott , Drew C. Ness , David J. Lilja MEMESTAR: A Simulation Framework for Reliability Evaluation over Multiple Environments. [Citation Graph (0, 0)][DBLP ] Conf ] 