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Publications of Author

1. Clive Bittlestone, Anthony M. Hill, Vipul Singhal, N. V. Arvind
   Architecting ASIC libraries and flows in nanometer era. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:776-781 [Conf]
   
2. Jayashree Saxena, Kenneth M. Butler, Vinay B. Jayaram, Subhendu Kundu, N. V. Arvind, Pravin Sreeprakash, Manfred Hachinger
   A Case Study of IR-Drop in Structured At-Speed Testing. [Citation Graph (0, 0)][DBLP]
   ITC, 2003, pp:1098-1104 [Conf]
   
3. N. V. Arvind, P. R. Suresh, V. Sivakumar, Chandrani Pal, Debaprasad Das
   Integrated Crosstalk And Oxide Integrity Analysis In Dsm Designs. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2001, pp:518-523 [Conf]
   
4. N. V. Arvind, K. A. Rajagopal, H. S. Ajith, Das Suparna
   Path Based Approach for Crosstalk Delay Analysis. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2004, pp:727-730 [Conf]
   
5. K. A. Rajagopal, R. Sivakumar, N. V. Arvind, C. Sreeram, Vish Visvanathan, Shailendra Dhuri, Roopesh Chander, Patrick Fortner, Subra Sripada, Qiuyang Wu
   A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay Signoff. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2006, pp:277-282 [Conf]
   
6. Sachin Shrivastava, Dhanoop Varghese, Vikas Narang, N. V. Arvind
   Improved Approach for Noise Propagation to Identify Functional Noise Violations. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2004, pp:705-708 [Conf]
   
7. 
   Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations. [Citation Graph (, )][DBLP]
   
   
8. 
   An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis. [Citation Graph (, )][DBLP]