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Conferences in DBLP

VLSI Design (vlsid)
2006 (conf/vlsid/2006)


  1. Organizing Committee. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:- [Conf]

  2. Conference Committee. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:- [Conf]

  3. VLSI Design 2005 Conference Awards. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:- [Conf]

  4. VLSI Design 2006 Conference Awards. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:- [Conf]

  5. Reviewers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:- [Conf]

  6. Message from the Organizing Chair. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:- [Conf]

  7. VLSI Design Conference History. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:- [Conf]

  8. Embedded Systems Design Conference History. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:- [Conf]

  9. Call for Participation: VLSI Design 2007. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:- [Conf]

  10. Call for Participation: 10th IEEE VLSI Design & Test Symposium. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:- [Conf]

  11. Message from the General Chairs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:- [Conf]

  12. Message from the Program Chairs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:- [Conf]

  13. Program Committee. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:- [Conf]
  14. A. V. S. S. Prasad, Jacob Mathews, Nagi Naganathan
    Low-Power Design Strategies for Mobile Computing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:3-4 [Conf]
  15. Ruchir Puri, Tanay Karnik, Rajiv V. Joshi
    Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:5-7 [Conf]
  16. Shiv Tasker, Rishiyur S. Nikhil
    Beyond RTL: Advanced Digital System Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:8-9 [Conf]
  17. Shanthi Pavan, Prakash Easwaran, C. Srinivasan
    System Aspects of Analog to Digital Converter Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:10- [Conf]
  18. N. S. Nagaraj
    Interconnect Process Variations: Theory and Practice. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:11- [Conf]
  19. Goutam Debnath, Paul J. Thadikaran
    Design Challenges for High Performance Nano-Technology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:12-13 [Conf]
  20. David Abercrombie, Bernd Koenemann, Nagesh Tamarapalli, Srikanth Venkataraman
    DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:14- [Conf]
  21. R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopal, N. Guruprasad, K. Subbarangaiah, Taher Abbasi, D. V. R. Murthy, P. Krishna Prasad, D. R. Gude
    A Comprehensive SoC Design Methodology for Nanometer Design Challenges. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:15-17 [Conf]
  22. Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra
    Sequential Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:18-19 [Conf]
  23. Parimal Patel
    Embedded Systems Design Using FPGA. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:20- [Conf]
  24. Robert C. Lacovara, Dhadesugoor R. Vaman
    Design of Embedded Systems with Novel Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:21-22 [Conf]
  25. David E. Orton
    Small, Smart, Intelligent and Interactive Handheld Devices. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:25- [Conf]
  26. Richard Miller
    We Want It All, and We Want It Now! [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:29- [Conf]
  27. Matthew Rhodes
    Keynote Address. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:30- [Conf]
  28. Henry Potts
    IC/FPGA-Package-PCB Design Collaboration. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:31- [Conf]
  29. Jackson Hu
    The Technological and Geographical Migration of the Semiconductor Industry. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:35- [Conf]
  30. Richard Sevcik
    Future FPGA Technologies, in Partnership with Universities. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:36- [Conf]
  31. Arvind
    UNUM: A Tinker-Toy Approach to Building Multicore PowerPC Microarchitectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:39- [Conf]
  32. Mahesh Mehendale
    SoC - The Road Ahead. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:40- [Conf]
  33. Andreas Kuehlmann
    Integrated Design Flows - A Battered EDA Slogan or True Challenge for Tool Development and Algorithmic Research. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:41- [Conf]
  34. K. Narasimhulu, V. Ramgopal Rao
    Embedded Tutorial: Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:45-50 [Conf]
  35. M. S. Bhat, S. Rekha, H. S. Jamadagni
    Extrinsic Analog Synthesis Using Piecewise Linear Current-Mode Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:51-56 [Conf]
  36. Prabir K. Saha, Ashudeb Dutta, A. Patra, T. K. Bhattacharyya
    Design of a 1 V Low Power 900 MHz QVCO. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:57-62 [Conf]
  37. Gaurav Raja, Basabi Bhaumik
    16-Bit Segmented Type Current Steering DAC for Video Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:63-68 [Conf]
  38. Subhadeep Banik, Daibashish Gangopadhyay, T. K. Bhattacharyya
    A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in 0.18µ Digital CMOS. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:69-74 [Conf]
  39. Koushik De, Santiram Kal
    A Low Power 6-Bit A/D Converter Achieving 10-Bit Resolution for MEMS Sensor Interface Using Time-Interleaved Delta Modulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:75-80 [Conf]
  40. Saraju P. Mohanty, Elias Kougianos
    Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:83-88 [Conf]
  41. Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown
    Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:89-93 [Conf]
  42. Thara Rejimon, Sanjukta Bhanja
    Wide Limited Switch Dynamic Logic Circuit Implementations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:94-99 [Conf]
  43. Mohammad Gh. Mohammad, Laila Terkawi, Muna Albasman
    A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:100-107 [Conf]
  44. M. Jagadesh Kumar, Ali A. Orouji
    Phase Change Memory Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:108-112 [Conf]
  45. Peter Caputa, Christer Svensson
    A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:117-122 [Conf]
  46. Min Tang, Jun-Fa Mao
    Optimization of Global Interconnects in High Performance VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:123-128 [Conf]
  47. Shabbir H. Batterywala, Rohit Ananthakrishna, Yansheng Luo, Alex Gyure
    A Statistical Method for Fast and Accurate Capacitance Extraction in the Presence of Floating Dummy Fills. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:129-134 [Conf]
  48. Rohit Ananthakrishna, Shabbir H. Batterywala
    MoM - A Process Variation Aware Statistical Capacitance Extractor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:135-140 [Conf]
  49. Amitava Bhaduri, Ranga Vemuri
    Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:141-146 [Conf]
  50. Jin-Tai Yan, Chia-Fang Lee, Yen-Hsiang Chen
    Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:147-152 [Conf]
  51. Tathagato Rai Dastidar, Partha Ray
    A New Device Level Digital Simulator for Simulation and Functional Verification of Large Semiconductor Memories. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:155-160 [Conf]
  52. Hari Vijay Venkatanarayanan, Michael L. Bushnell
    An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:161-168 [Conf]
  53. Dong Hyun Baik, Kewal K. Saluja
    Test Cost Reduction Using Partitioned Grid Random Access Scan. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:169-174 [Conf]
  54. Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya
    An Efficient Scan Tree Design for Compact Test Pattern Set. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:175-180 [Conf]
  55. Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang
    On Methods to Improve Location Based Logic Diagnosis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:181-187 [Conf]
  56. Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil
    Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:188-193 [Conf]
  57. V. Ramakrishnan, Poras T. Balsara
    A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:197-202 [Conf]
  58. Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
    Programmable LDPC Decoder Based on the Bubble-Sort Algorithm. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:203-208 [Conf]
  59. Simon Hollis, Simon W. Moore
    An Asynchronous Interconnect Architecture for Device Security Enhancement. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:209-215 [Conf]
  60. Tong Zhou, Mingyan Yu, Yizheng Ye
    A Pipelined Switched-Current Chaotic System for the High-Speed Truly Random Number Generation in Crypto Processor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:216-221 [Conf]
  61. Qiang Qiang, Daniel G. Saab, Jacob A. Abraham
    Checking Nested Properties Using Bounded Model Checking and Sequential ATPG. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:225-230 [Conf]
  62. Praveen Tiwari, Saptarshi Biswas, Raj S. Mitra
    Apriori Formal Coverage Analysis for Protocol Properties. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:231-236 [Conf]
  63. Rolf Drechsler, Görschwin Fey, Sebastian Kinder
    An Integrated Approach for Combining BDD and SAT Provers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:237-242 [Conf]
  64. Aman Kokrady, Theo J. Powell, S. Ramakrishnan
    Reducing Design Verification Cycle Time through Testbench Redundancy. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:243-248 [Conf]
  65. Xin Jia, Ranga Vemuri
    CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:251-256 [Conf]
  66. Yan Feng, Dinesh P. Mehta
    Heterogeneous Floorplanning for FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:257-262 [Conf]
  67. Mark P. Tennant, Ahmet T. Erdogan, Tughrul Arslan, John S. Thompson
    A Novel Architecture Using the Decorrelating Transform for Low Power Adaptive Filters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:263-268 [Conf]
  68. Amit Kumar 0002, Noriyuki Miura, Muhammad Muqsith, Tadahiro Kuroda
    Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:271-276 [Conf]
  69. K. A. Rajagopal, R. Sivakumar, N. V. Arvind, C. Sreeram, Vish Visvanathan, Shailendra Dhuri, Roopesh Chander, Patrick Fortner, Subra Sripada, Qiuyang Wu
    A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay Signoff. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:277-282 [Conf]
  70. Narender Hanchate, Nagarajan Ranganathan
    A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:283-290 [Conf]
  71. Samik Das, P. P. Chakrabarti, Pallab Dasgupta
    Instruction-Set-Extension Exploration Using Decomposable Heuristic Search. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:293-298 [Conf]
  72. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
    Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:299-304 [Conf]
  73. Biman Chakraborty, Ting Chen, Tulika Mitra, Abhik Roychoudhury
    Handling Constraints in Multi-Objective GA for Embedded System Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:305-310 [Conf]
  74. Ahsan Raja Chowdhury, Rumana Nazmul, Hafiz Md. Hasan Babu
    A New Approach to Synthesize Multiple-Output Functions Using Reversible Programmable Logic Array. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:311-316 [Conf]
  75. Rui Zhang, Niraj K. Jha
    State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:317-322 [Conf]
  76. Jayashree Sridharan, Tom Chen
    Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:323-328 [Conf]
  77. R. G. Raghavendra, Pradip Mandal
    An On-Chip Voltage Regulator with Improved Load Regulation and Light Load Power Efficiency. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:331-336 [Conf]
  78. Puneet Gupta, Andrew B. Kahng
    Efficient Design and Analysis of Robust Power Distribution Meshes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:337-342 [Conf]
  79. Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu
    Test Pattern Generation for Power Supply Droop Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:343-348 [Conf]
  80. Baohua Wang, Pinaki Mazumder
    Bounding Supply Noise Induced Path Delay Variation Using a Relaxation Approach. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:349-354 [Conf]
  81. Subodh M. Reddy, Rajeev Murgai
    Accurate Substrate Noise Analysis Based on Library Module Characterization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:355-362 [Conf]
  82. Venkat Rao Vallapenani, Ravi Shankar Chevuri, Bingxiong Xu, Lun Ye, Kanad Chakraborty
    Efficient Techniques for Noise Characterization of Sequential Cells and Macros. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:363-368 [Conf]
  83. Soumyajit Dey, Susmit Biswas, Arijit Mukhopadhyay, Anupam Basu
    An Approach to Architectural Enhancement for Embedded Speech Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:371-376 [Conf]
  84. Jun Chen, Rong Luo, Huazhong Yang, Hui Wang
    A Low Power ROM-Less Direct Digital Frequency Synthesizer with Preset Value Pipelined Accumulator. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:377-380 [Conf]
  85. Rama Sangireddy, Prabhu Rajamani, Shwetha Gaddam
    Performance Optimization with Scalable Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:381-386 [Conf]
  86. Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas
    Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:387-392 [Conf]
  87. V. Mahalingam, N. Ranganathan
    An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:393-398 [Conf]
  88. Higinio Mora Mora, Jerónimo Mora Pascual, J. L. Sánchez Romero, F. Pujol Lóópez
    Partial Product Reduction Based on Look-Up Tables. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:399-404 [Conf]
  89. Suresh Kumar Devanathan, Michael L. Bushnell
    Sequential Spectral ATPG Using the Wavelet Transform and Compaction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:407-412 [Conf]
  90. Shweta Chary, Michael L. Bushnell
    Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:413-418 [Conf]
  91. Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
    New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:419-424 [Conf]
  92. Kalyana R. Kantipudi
    On the Size and Generation of Minimal N-Detection Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:425-430 [Conf]
  93. Loganathan Lingappan, Niraj K. Jha
    Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:431-436 [Conf]
  94. Achintya Halder, Abhijit Chatterjee
    Low-Cost Production Testing of Wireless Transmitters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:437-442 [Conf]
  95. Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
    Double-Gate SOI Devices for Low-Power and High-Performance Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:445-452 [Conf]
  96. Ali Javey, Hongjie Dai
    Carbon Nanotube Electronics. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:453-458 [Conf]
  97. Ivan Radojevic, Zoran A. Salcic, Partha S. Roop
    Design of Heterogeneous Embedded Systems Using DFCharts Model of Computation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:461-464 [Conf]
  98. David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee
    Dynamic Template Generation for Resource Sharing in Control and Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:465-468 [Conf]
  99. Anirban Lahiri, Saurabh Agarwal, Anupam Basu, Bhargab B. Bhattacharya
    Recovery-Based Real-Time Static Scheduling for Battery Life Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:469-472 [Conf]
  100. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:473-476 [Conf]
  101. Viswanath Sairaman, Nagarajan Ranganathan, Neeta S. Singh
    An Automatic Code Generation Tool for Partitioned Software in Distributed Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:477-480 [Conf]
  102. Naga M. Kosaraju, Murali Varanasi, Saraju P. Mohanty
    A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:481-484 [Conf]
  103. Motoi Ichihashi, Haruki Toda
    Performance Measurement and Improvement of Asymmetric Three-Tr. Cell (ATC) DRAM toward 0.3V Memory Array Operation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:487-490 [Conf]
  104. Ashok Narasimhan, Bhooma Srinivasaraghavan, Ramalingam Sridhar
    A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:491-494 [Conf]
  105. Sanjeev K. Jain, Pankaj Agarwal
    A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:495-498 [Conf]
  106. R. Rajaraman, J. S. Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    SEAT-LA: A Soft Error Analysis Tool for Combinational Logic. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:499-502 [Conf]
  107. Siva Embanath, Ramakrishnan Venkata
    Exceptional ASIC: Through Automatic Timing Exception Generation (ATEG). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:503-506 [Conf]
  108. Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti
    An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:507-510 [Conf]
  109. Alok Kumar Pani, Ratnam V. Raja Kumar
    Optimized VLIW Architecture for Non-zero IF QAM-Modem Implementations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:513-516 [Conf]
  110. Kavish Seth, K. N. Viswajith, S. Srinivasan, V. Kamakoti
    Ultra Folded High-Speed Architectures for Reed-Solomon Decoders. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:517-520 [Conf]
  111. Mian Dong, Chun Zhang, Songping Mai, Zhihua Wang, Dongmei Li
    A Wideband Frequency-Shift Keying Demodulator for Wireless Neural Stimulation Microsystems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:521-524 [Conf]
  112. Simon Ogg, Bashir M. Al-Hashimi
    Improved Data Compression for Serial Interconnected Network on Chip through Unused Significant Bit Removal. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:525-529 [Conf]
  113. Anand Gautam, A. Geeta Madhuri, Priya Khandelwal, K. Pratyush Aditya, Meghana Desai, Padma N. Krishna, Malvika Dutt, Reeti Bhatia
    Novel Architecture of EBC for JPEG2000. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:530-533 [Conf]
  114. J. Bhattacharyya, P. Mandal, R. Banerjee, Swapna Banerjee
    Real Time Dynamic Receive Apodization for an Ultrasound Imaging System. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:534-537 [Conf]
  115. Rajendra M. Patrikar, Olivier Peyran
    Design Planning for Uniform Thermal Distribution. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:541-544 [Conf]
  116. Subhashis Majumder, Bhargab B. Bhattacharya
    Solving Thermal Problems of Hot Chips Using Voronoi Diagrams. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:545-548 [Conf]
  117. Deepanjan Datta, Samiran Ganguly
    Design of Multi-bit SET Adder and Its Fault Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:549-552 [Conf]
  118. Mengmeng Ding, Ranga Vemuri
    Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:553-556 [Conf]
  119. Qadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri
    A Single Supply Level Shifter for Multi-Voltage Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:557-560 [Conf]
  120. Zhiyuan Li, Mingyan Yu, Jianguo Ma
    A Rail-to-Rail I/O Operational Amplifier with 0.5% gm Fluctuation Using Double P-channel Differential Input Pairs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:563-568 [Conf]
  121. Srikanth Sundaram, Praveen Elakkumanan, Ramalingam Sridhar
    High Speed Robust Current Sense Amplifier for Nanoscale Memories: - A Winner Take All Approach. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:569-574 [Conf]
  122. Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran
    ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:575-580 [Conf]
  123. Qadeer Ahmad Khan, G. K. Siddhartha, Divya Tripathi, Sanjay Kumar Wadhwa, Kulbhushan Misri
    Techniques for On-Chip Process Voltage and Temperature Detection and Compensation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:581-586 [Conf]
  124. Debashis Dutta, Ritesh Ujjwal, Swapna Banerjee
    Design of Low-Voltage Low-Power Continuous-Time Filter for Hearing Aid Application Using CMOS Current Conveyor Based Translinear Loop. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:587-592 [Conf]
  125. Sanjoy Kr. Dey, Swapna Banerjee
    An 8-Bit, 3.8GHz Dynamic BiCMOS Comparator for High-Performance ADC. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:593-598 [Conf]
  126. K. Sadeghi, M. Emadi, F. Farbiz
    Using Level Restoring Method for Dual Supply Voltage. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:601-605 [Conf]
  127. Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak
    Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:606-612 [Conf]
  128. Koushik Maharatna, Alfonso Troya, Milos Krstic, Eckhard Grass
    On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:613-618 [Conf]
  129. Sushanta K. Mandal, Arijit De, Amit Patra, Shamik Sural
    A Wide-Band Lumped Element Compact CAD Model of Si-Based Planar Spiral Inductor for RFIC Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:619-624 [Conf]
  130. G. Girishankar, Shitanshu Tiwari
    Generating Scalable Polynomial Models: Key to Low Power High Performance Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:625-630 [Conf]
  131. Sanjay Kumar Wadhwa, G. K. Siddhartha, Anand Gaurav
    Zero Steady State Current Power on Reset Circuit with Brown-Out Detector. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:631-636 [Conf]
  132. Haris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar
    Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:639-644 [Conf]
  133. Viswanathan Lakshmi Prabha, Elwin Chandra Monie
    Reinforcement Temporal Difference Learning Scheme for Dynamic Energy Management in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:645-650 [Conf]
  134. Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
    Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:651-656 [Conf]
  135. Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal
    A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:657-664 [Conf]
  136. Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
    Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:667-671 [Conf]
  137. Gurpreet Shinh, Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Ihsan Erdin
    Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:672-676 [Conf]
  138. Arnab Sarkar, P. P. Chakrabarti, Rajeev Kumar
    Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:677-682 [Conf]
  139. Sandip Aine, P. P. Chakrabarti, Rajeev Kumar
    Improving the Performance of CAD Optimization Algorithms Using On-Line Meta-Level Control. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:683-688 [Conf]
  140. Ritochit Chakraborty, Mukesh Ranjan, Ranga Vemuri
    Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:689-694 [Conf]
  141. Gaurav Trivedi, Madhav P. Desai, H. Narayanan
    Fast DC Analysis and Its Application to Combinatorial Optimization Problems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:695-700 [Conf]
  142. Mircea R. Stan, Garrett S. Rose, Matthew M. Ziegler
    Hybrid CMOS/Molecular Electronic Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:703-708 [Conf]
  143. Vivek Subramanian, Paul C. Chang, Daniel Huang, Josephine B. Lee, Steven E. Molesa, David R. Redinger, Steven K. Volkman
    All-Printed RFID Tags: Materials, Devices, and Circuit Implications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:709-714 [Conf]
  144. Roopak Suri, C. M. Markan
    Threshold Trimming Based Design of a CMOS Programmable Operational Amplifier. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:717-720 [Conf]
  145. T. K. Bhattacharyya, Shreyas Sen, Debashis Mandal, S. K. Lahiri
    Development of a Wireless Integrated Toxic and Explosive MEMS Based Gas Sensor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:721-724 [Conf]
  146. Evangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson
    Custom Reconfigurable Architecture for Autonomous Fault-Recovery of MEMS Vibratory Sensor Electronics. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:725-728 [Conf]
  147. Soumendu Bhattacharya, Vishwanath Natarajan, Abhijit Chatterjee, Sankar Nair
    Efficient DNA Sensing with Fabricated Silicon Nanopores: Diagnosis Methodology and Algorithms. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:729-733 [Conf]
  148. Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan
    Area and Power Efficient VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:734-737 [Conf]
  149. Supriya S. Shanbhag
    CMOS Integrated Circuit for Sensing Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:738-741 [Conf]
  150. V. S. Kanchana Bhaaskaran, S. Salivahanan, D. S. Emmanuel
    Semi-Custom Design of Adiabatic Adder Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:745-748 [Conf]
  151. Abdelhalim Alsharqawi, Abdel Ejnioui
    Clockless Pipelining for Coarse Grain Datapaths. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:749-753 [Conf]
  152. Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara
    Exploring Logic Block Granularity in Leakage Tolerant FPGA. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:754-757 [Conf]
  153. Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang
    High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:758-761 [Conf]
  154. Yen-Jen Chang
    An Alternative Real-Time Filter Scheme to Block Buffering. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:762-765 [Conf]
  155. Aswath Oruganti, Nagarajan Ranganathan
    Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:766-769 [Conf]
  156. Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis
    Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:773-776 [Conf]
  157. Alkan Cengiz, Tom Chen
    A Progressive Two-Stage Global Routing for Macro-Cell Based Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:777-780 [Conf]
  158. Suresh Balasubramanian, Narayanan Natarajan, Olivier Franza, Chris Gianos
    Deterministic Low-Latency Data Transfer across Non-Integral Ratio Clock Domains. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:781-785 [Conf]
  159. Usha Narasimha, Anthony M. Hill, N. S. Nagaraj
    SmartExtract: Accurate Capacitance Extraction for SOC Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:786-789 [Conf]
  160. Parthasarathi Dasgupta, Prashant Yadava
    Linear Required-Arrival-Time Trees and their Construction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:790-793 [Conf]
  161. Snehashis Roy, S. Jairam, H. Udayakumar
    A Methodology for Switching Activity Based IO Powerpad Optimisation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:794-797 [Conf]
  162. Omar I. Khan, Michael L. Bushnell
    Aliasing Analysis of Spectral Statistical Response Compaction Techniques. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:801-806 [Conf]
  163. Priya Iyer, Shailendra Jain, Bryan Casper, Jason Howard
    Testing High-Speed IO Links Using On-Die Circuitry. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:807-810 [Conf]
  164. Kedarnath J. Balakrishnan, Seongmoon Wang, Srimat T. Chakradhar
    PIDISC: Pattern Independent Design Independent Seed Compression Technique. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:811-817 [Conf]
  165. Shweta Chary, Michael L. Bushnell
    Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:818-823 [Conf]
  166. Ramesh C. Tekumalla
    An On-Chip Diagnosis Methodology for Embedded Cores with Replaceable Modules. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:824-827 [Conf]
  167. Irith Pomeranz, Sudhakar M. Reddy
    The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:828-831 [Conf]
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