The SCEAS System
Navigation Menu

Search the dblp DataBase


Raghuram S. Tupuri: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. Abraham
    Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:647-652 [Conf]
  2. Jacob A. Abraham, Arun Krishnamachary, Raghuram S. Tupuri
    A Comprehensive Fault Model for Deep Submicron Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:360-364 [Conf]
  3. Raghuram S. Tupuri, Jacob A. Abraham
    A Novel Functional Test Generation Method for Processors Using Commercial ATPG. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:743-752 [Conf]
  4. Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri
    Delay Constrained Register Transfer Level Dynamic Power Estimation. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:36-46 [Conf]
  5. Arun Krishnamachary, Jacob A. Abraham, Raghuram S. Tupuri
    Timing Verification and Delay Test Generation for Hierarchical Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:157-162 [Conf]
  6. Raghuram S. Tupuri, Jacob A. Abraham
    A Novel Hierarchical Test Generation Method for Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:540-541 [Conf]
  7. Raghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab
    Hierarchical Test Generation for Systems On a Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:198-0 [Conf]

  8. A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits. [Citation Graph (, )][DBLP]

Search in 0.003secs, Finished in 0.004secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002