Conferences in DBLP
Mike W. T. Wong , K. Y. Ko , Y. S. Lee Analog and Mixed-Signal IP Cores Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Hans G. Kerkhoff , Arun A. Joseph , Sander Heuvelmans Testable Design and Testing of High-Speed Superconductor Microelectronics. [Citation Graph (0, 0)][DBLP ] Conf ] Zhen Guo , Jacob Savir Observer-Based Test of Analog Linear Time-Invariant Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gloria Huertas , Diego Vázquez , Adoración Rueda , José L. Huertas Practical Oscillation-Based Test in Analog Integrated Filters: Experimental Results. [Citation Graph (0, 0)][DBLP ] Conf ] Soumendu Bhattacharya , Abhijit Chatterjee Constrained Specification-Based Test Stimulus Generation for Analog Circuits Using Nonlinear Performance Prediction Models. [Citation Graph (0, 0)][DBLP ] Conf ] Ruly Lai-U Choi , Ross D. Murch MIMO Transmit Optimization for Wireless Communication Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Tharek Abdul Rahman , Toh Chee Leng Adaptive Power Control Design for Microwave Communication System. [Citation Graph (0, 0)][DBLP ] Conf ] Salim Ouadjaout , Marie-France Albenge , Dominique Houzet VSIA Interface Cosynthesis. [Citation Graph (0, 0)][DBLP ] Conf ] J. Y. Khan , J. Wall , M. A. Rashid Bluetooth-Based Wireless Personal Area Network for Multimedia Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Florent Carlier , Fabienne Nouvel , Jacques Citerne Multi-User Detection for CDMA Communications Based on Self Organized Neural Networks Structures. [Citation Graph (0, 0)][DBLP ] Conf ] J. Geoffrey Chase , Christopher Pretty , Alex Bedarida , Philippe Bettler An Applications-Based Approach to Measuring DSP Efficiency. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher Pretty , J. Geoffrey Chase Reconfigurable DSP's for Efficient MPEG-4 Video and Audio Decoding. [Citation Graph (0, 0)][DBLP ] Conf ] Peter J. Green , Desmond P. Taylor Smart Antenna Software Radio Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Victor Varshavsky , Vyacheslav Marakhovsky GALA Approach in Design of Asynchronous Control for Counterflow Pipeline Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Dominique Federici , Paul Bisgambiglia , Jean François Santucci Behavioral Fault Simulation: Implementation and Experiments Results. [Citation Graph (0, 0)][DBLP ] Conf ] Raimund Ubar , Jaan Raik , Eero Ivask , Marina Brik Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuya Shimizu , Masaya Takamura , Takanori Shirai , Noriyoshi Itazaki , Kozo Kinoshita Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Haifeng Zhou , Zhenghui Lin , Wei Cao Research on VHDL RTL Synthesis System. [Citation Graph (0, 0)][DBLP ] Conf ] Amjad Hajjar , Tom Chen An Accurate Coverage Forecasting Model for Behavioral Model Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Chie Dou , Shing-Jeh Jiang , Kuo-Cheng Leu A Novel CAM/RAM Based Buffer Manager for Next Generation IP Routers. [Citation Graph (0, 0)][DBLP ] Conf ] Ilkka Saastamoinen , David A. Sigüenza-Tortosa , Jari Nurmi Interconnect IP Node for Future System-on-Chip Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg E. Vollrath Signal Margin Analysis for Memory Sense Amplifiers . [Citation Graph (0, 0)][DBLP ] Conf ] A. J. van de Goor , Ivo Schanstra Address and Data Scrambling: Causes and Impact on Memory Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Jen-Chieh Yeh , Chi-Feng Wu , Kuo-Liang Cheng , Yung-Fa Chou , Chih-Tsun Huang , Cheng-Wen Wu Flash Memory Built-In Self-Test Using March-Like Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Atsumu Iseno , Yukihiro Iguchi A Method for Storing Fail Bit Maps in Burn-in Memory Testers. [Citation Graph (0, 0)][DBLP ] Conf ] Phillip E. Pascoe , Harsha Sirisena , Adnan H. Anbuky Coup De Fouet Based VRLA Battery Capacity Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Chandramouli Gopalakrishnan , Srinivas Katkoori Power Optimization of Combinational Circuits by Input Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Ranganathan Sankaralingam , Nur A. Touba Reducing Test Power During Test Using Programmable Scan Chain Disable. [Citation Graph (0, 0)][DBLP ] Conf ] Meng-Lieh Sheu , Tai-Ping Sun , Far-Wen Jih Test Socket Chip for Measuring Dark Current in IR FPA. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Wen Lu , Chung-Len Lee A Low Power High Speed Class-B Buffer Amplifier for Flat Panel Display Application. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Yaw Chung , Mao-Hsiang Yeh , Jia-Chyi Chen , Shen-Kan Hsiung , Dorota G. Pijanowska , Wladyslaw Torbicz , Jung-Chuan Chou , Tai-Ping Sun Design of a Low-voltage Instrumentation Amplifier for Enzyme-Extended-Gate Field Effect Transistor Based Urea Sensor Application. [Citation Graph (0, 0)][DBLP ] Conf ] Ranjit Singh , Low Lee Ngo , Ho Soon Seng , Frederick Neo Chwee Mok A Silicon Piezoresistive Pressure Sensor. [Citation Graph (0, 0)][DBLP ] Conf ] César A. Piña Evolution Of The Mosis VLSI Educational Program. [Citation Graph (0, 0)][DBLP ] Conf ] David V. Kerns , Sherra E. Kerns , Gill A. Pratt , Mark H. Somerville , Jill D. Crisman The Search for Design in Electrical Engineering Education. [Citation Graph (0, 0)][DBLP ] Conf ] R. M. Hodgson The Development and Transfer of Advanced Technology from Universities to Industry. [Citation Graph (0, 0)][DBLP ] Conf ] Ton J. Mouthaan , R. W. Brink , Henk Vos Competencies of BSc and MSc Programmes in Electrical Engineering and Student Portfolios. [Citation Graph (0, 0)][DBLP ] Conf ] Dale A. Carnegie Electronics Education: A Systems Based Mechatronic Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Rucinski , Barbara Dziurla-Rucinska Boundary Scan as a Test Solution in Microelectronics Curricula. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Moorhead , Serge N. Demidenko Making ATE Accessible for Academic Institutions. [Citation Graph (0, 0)][DBLP ] Conf ] Richard J. Blaikie , Maan M. Alkaisi , Steven M. Durbin , David R. S. Cumming Teaching Integrated Circuit and Semiconductor Device Design in New Zealand: The University of Canterbury Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Yves Bertrand , Marie-Lise Flottes , Florence Azaïs , Serge Bernard , Laurent Latorre , Regis Lorival European Network for Test Education. [Citation Graph (0, 0)][DBLP ] Conf ] Yao Li , Paul Wilson PARTOS-11: an Efficient Real-Time Operating System for Low-Cost Microcontrollers. [Citation Graph (0, 0)][DBLP ] Conf ] Murray Pearson , Dean Armstrong , Tony McGregor Design of a Processor to Support the Teaching of Computer Systems. [Citation Graph (0, 0)][DBLP ] Conf ] John L. Bähr Applied Science (Electronics) at the University of Otago. [Citation Graph (0, 0)][DBLP ] Conf ] R. Browne , Serge N. Demidenko , R. O'Driscoll Harnessing Geographically Distributed Cooperation in Microtechnology Course at Massey University. [Citation Graph (0, 0)][DBLP ] Conf ] William Chen , Simon Round , Richard Duke Design of an Auxiliary Power Distribution Network for an Electric Vehicl. [Citation Graph (0, 0)][DBLP ] Conf ] Ibrahim H. Al-Bahadly Analysis of Position Estimation Method for Switched Reluctance Drives. [Citation Graph (0, 0)][DBLP ] Conf ] István Vajda Conceptual Design of an All Superconducting Mini Power Plant Model. [Citation Graph (0, 0)][DBLP ] Conf ] H. Hauser , P. Fulmek , F. Himmelstoss , T. Wolbank , R. Wöhrnschimmel , Peter R. Wurm Magnetic Hysteresis Modeling of Electronic Components. [Citation Graph (0, 0)][DBLP ] Conf ] David Parker Computer Based Real-Time Simulator for Renewable Energy Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Parag K. Lala , K. K. Bondali On Biologically-Inspired Design of Fault-Tolerant Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Anna Antola , Mariagiovanna Sami , Vincenzo Piuri On-line Diagnosis and Reconfiguration of FPGA Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell , Penelope Faure , Paolo Prinetto , Yervant Zorian Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Monica Alderighi , Fabio Casini , Sergio D'Angelo , Davide Salvi , Giacomo R. Sechi A Fault-Tolerant FPGA-based Multi-Stage Interconnection Network for Space Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg Velten , Anton Kummert FPGA-Based Implementation of Variable Sized Structuring Elements for 2D Binary Morphological Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Krips , Thomas Lammert , Anton Kummert FPGA Implementation of a Neural Network for a Real-Time Hand Tracking System. [Citation Graph (0, 0)][DBLP ] Conf ] Serge N. Demidenko , Rauf Kh. Sadykhov , Alexey N. Klimovich , Leonid P. Podenok , Maxim E. Vatkin Neural Networks to Solve the Problems of Control and Identification. [Citation Graph (0, 0)][DBLP ] Conf ] Rui Xiao , Chip-Hong Chang , Thambipillai Srikanthan On the Initialization and Training Methods for Kohonen Self-Organizing Feature Maps in Color Image Quantization. [Citation Graph (0, 0)][DBLP ] Conf ] Saeid Sanei , Tracey Kah-Mein Lee An Architecture for High Speed Ultrasound Image Capture and Real-time 3D Reconstruction. [Citation Graph (0, 0)][DBLP ] Conf ] Sourav Kundu , Kazuto Seto , Shigeru Sugino Genetic Algorithm Application to Vibration Control of Tall Flexible Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Gourab Sen Gupta , H. L. Sng , Chris H. Messom State Transition Based Supervisory Control for a Robot Soccer System. [Citation Graph (0, 0)][DBLP ] Conf ] Dale A. Carnegie A Semi-Generic System for the Control of Autonomous Mobile Mechatrons. [Citation Graph (0, 0)][DBLP ] Conf ] H. L. Sng , Gourab Sen Gupta , Chris H. Messom Strategy for Collaboration in Robot Soccer. [Citation Graph (0, 0)][DBLP ] Conf ] Nasser Masoumi , Mohamed I. Elmasry , Safieddin Safavi-Naeini , Haydar Hadi A Novel Analytical Model for Evaluation of Substrate Crosstalk in VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob A. Abraham , Arun Krishnamachary , Raghuram S. Tupuri A Comprehensive Fault Model for Deep Submicron Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Seung Hoon Choi , Kaushik Roy Noise Analysis under Capacitive and Inductive Coupling for High Speed Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel A. d'Abreu Noise-Its Sources, and Impact on Design and Test of Mixed Signal Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Properties of Output Sequences and their Use in Guiding Property-Based Test Generation for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Paoli , Marie-Laure Nivet , Jean François Santucci , Antoine Campana Path-Oriented Test Data Generation of Behavioral VHDL Description. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Yotsuyanagi , Masaki Hashizume , Taisuke Iwakiri , Masahiro Ichimiya , Takeomi Tamesada Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field. [Citation Graph (0, 0)][DBLP ] Conf ] Kohei Miyase , Seiji Kajihara , Sudhakar M. Reddy A Method of Static Test Compaction Based on Don't Care Identification. [Citation Graph (0, 0)][DBLP ] Conf ] Hideyuki Ichihara , Tomoo Inoue Generating Small Test Sets for Test Compression/Decompression Scheme Using Statistical Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Chehab , Rafic Z. Makki , Michael Spica , David Wu IDDT Test Methodologies for Very Deep Sub-micron CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gabriela Peretti , Eduardo Romero , Franco Salvático , Carlos A. Marqués A Functional Approach to Test Cascaded BCD Counters. [Citation Graph (0, 0)][DBLP ] Conf ] Seiji Kajihara , Kenjiro Taniguchi , Irith Pomeranz , Sudhakar M. Reddy Test Data Compression Using Don't-Care Identification and Statistical Encoding. [Citation Graph (0, 0)][DBLP ] Conf ] S. M. Aziz , S. J. Carr On C-Testability of Carry Free Dividers. [Citation Graph (0, 0)][DBLP ] Conf ] S. C. Mukhopadhyay Modeling of a Repulsive Type Magnetic Bearing for Five Axis Control Under Intermittent Operation Including Eddy Current Effect. [Citation Graph (0, 0)][DBLP ] Conf ] C. Chakraborty , S. C. Mukhopadhyay A Novel Compound Type Resonant Rectifier Topology. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinobu Higami , Shin-ya Kobayashi , Yuzo Takamatsu Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Hlavicka , Petr Fiser Minimization and Partitioning Method Reducing Input Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Mirco Pieper , Anton Kummert Stand-alone Digital Real-Time Image Processing Board based on an FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Zoorina Bee Kader Mastan , Azrul Ghazali , Muhammad Muhsin Idris Transmission of Data/Sketch through Telephone Lines using Gapping Technique via a Low Cost Telewriting Equipment . [Citation Graph (0, 0)][DBLP ] Conf ] Matthew Worsman , Mike W. T. Wong , Y. S. Lee Enhancing The Static D. C. Fault Diagnosis Of A Resistance Temperature Detector Sensor Circuit Using Equivalent Fault Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Yannick Bonhomme , Patrick Girard , Christian Landrault , Serge Pravossoudovitch Test Power: a Big Issue in Large SOC Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Sébastien Mallier , Fabienne Nouvel , Jean-Yves Baudais , Daniel Gardan , Ahmed Zeddam Multi-Carrier CDMA over Copper Lines-Comparison of Performances with the ADSL System. [Citation Graph (0, 0)][DBLP ] Conf ] Leonardo L. Giovanini Multivariable Predictive Feedback Control. [Citation Graph (0, 0)][DBLP ] Conf ] Masaki Hashizume , Masashi Sato , Hiroyuki Yotsuyanagi , Takeomi Tamesada Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Sosnowski , K. Szafran Monitoring Parallel Interfaces in System Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Shing Tenqchen , Ji-Horn Chang , Wu-Shiung Feng , Bor-Sheng Jeng Pipelining Extended Givens Rotation RLS Adaptive Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Yong Liu , Zhiqiang Gao , Xiangqing He A Flexible Embedded SRAM Compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Piia Simonen , Ilkka Saastamoinen , Mika Kuulusa , Jari Nurmi Advanced Instruction Set Architectures for Reducing Program Memory Usage in a DSP Processor. [Citation Graph (0, 0)][DBLP ] Conf ] William Phipps , Ibrahim Al-Bahadly Sensorless Speed Control in Induction Motor Drives. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Gaynor , Jonathan Skipwith A High Voltage Amplifier for use in Medical Applications of Electroporation. [Citation Graph (0, 0)][DBLP ] Conf ] Adrian A. Dorrington , Rainer Künnemeyer A Simple Microcontroller Based Digital Lock-in Amplifier for the Detection of Low Level Optical Signals. [Citation Graph (0, 0)][DBLP ] Conf ] Ranjit Singh An Intelligent System for Odour Discrimination. [Citation Graph (0, 0)][DBLP ] Conf ] Warwick Allen , Donald Bailey , Serge N. Demidenko , Vincenzo Piuri Test Chirp Signal Generation Using Spectral Warping. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Gaur , Vishwani D. Agrawal , Michael L. Bushnell A New Transitive Closure Algorithm with Application to Redundancy Identification. [Citation Graph (0, 0)][DBLP ] Conf ] D. G. Bailey , D. Irecki , B. K. Lim , L. Yang Test Bed for Number Plate Recognition Applications. [Citation Graph (0, 0)][DBLP ] Conf ] S. M. Aziz , C. N. Basheer , Joarder Kamruzzaman A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] M. Walker , Chris H. Messom A Comparison of Genetic Programming and Genetic Algorithms for Auto-tuning Mobile Robot Motion Control. [Citation Graph (0, 0)][DBLP ] Conf ] 