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Publications of Author

1. Soontae Kim
   Area-efficient error protection for caches. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:1282-1287 [Conf]
   
2. Jie S. Hu, Narayanan Vijaykrishnan, Soontae Kim, Mahmut T. Kandemir, Mary Jane Irwin
   Scheduling Reusable Instructions for Power Reduction. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:148-155 [Conf]
   
3. Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, R. R. Brooks, Soontae Kim, Wei Zhang 0002
   Masking the Energy Behavior of DES Encryption. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10084-10089 [Conf]
   
4. Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin, Lizy Kurian John
   On load latency in low-power caches. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2003, pp:258-261 [Conf]
   
5. Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, E. Geethanjali
   Power-aware partitioned cache architectures. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2001, pp:64-67 [Conf]
   
6. Narayanan Vijaykrishnan, Mahmut T. Kandemir, Soontae Kim, Samarjeet Singh Tomar, Anand Sivasubramaniam, Mary Jane Irwin
   Energy Behavior of Java Applications from the Memory Perspective. [Citation Graph (0, 0)][DBLP]
   Java™ Virtual Machine Research and Technology Symposium, 2001, pp:207-220 [Conf]
   
7. Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin
   Partitioned instruction cache architecture for energy efficiency. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Embedded Comput. Syst., 2003, v:2, n:2, pp:163-185 [Journal]
   
8. J. Juran, Ali R. Hurson, Narayanan Vijaykrishnan, Soontae Kim
   Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues. [Citation Graph (0, 0)][DBLP]
   Wireless Networks, 2004, v:10, n:2, pp:183-195 [Journal]
   
9. Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin
   Reducing non-deterministic loads in low-power caches via early cache set resolution. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2007, v:31, n:5, pp:293-301 [Journal]
   
10. 
    SimTag: Exploiting tag bits similarity to improve the reliability of the data caches. [Citation Graph (, )][DBLP]
    
    
11. 
    Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system. [Citation Graph (, )][DBLP]
    
    
12. 
    Improving the reliability of on-chip L2 cache using redundancy. [Citation Graph (, )][DBLP]
    
    
13. 
    An energy-delay efficient 2-level data cache architecture for embedded system. [Citation Graph (, )][DBLP]
    
    
14. 
    Modeling and Evaluation of Control Flow Vulnerability in the Embedded System. [Citation Graph (, )][DBLP]
    
    
15. 
    Reducing ALU and Register File Energy by Dynamic Zero Detection. [Citation Graph (, )][DBLP]