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Publications of Author

1. Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman
   Reduced Delay Uncertainty in High Performance Clock Distribution Networks. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10068-10075 [Conf]
   
2. William R. Roberts, Dimitrios Velenis
   Effects of process and environmental variations on timing characteristics of clocked registers. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2006, pp:165-168 [Conf]
   
3. Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou
   A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2001, pp:422-425 [Conf]
   
4. Itisha Chanodia, Dimitrios Velenis
   Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2006, pp:456-457 [Conf]
   
5. Dimitris Velenis, Dimitris Kalogeras, Basil S. Maglaris
   SaTPEP: A TCP Performance Enhancing Proxy for Satellite Links. [Citation Graph (0, 0)][DBLP]
   NETWORKING, 2002, pp:1233-1238 [Conf]
   
6. Dimitrios Velenis, Eby G. Friedman
   Buffer Sizing for Crosstalk Induced Delay Uncertainty. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2004, pp:750-759 [Conf]
   
7. William R. Roberts, Dimitrios Velenis
   Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2005, pp:508-517 [Conf]
   
8. Boyan Semerdjiev, Dimitrios Velenis
   Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2007, pp:289-294 [Conf]
   
9. Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, V. Adler, F. Baez, Eby G. Friedman
   Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP]
   Journal of Circuits, Systems, and Computers, 2002, v:11, n:3, pp:231-246 [Journal]
   
10. Boyan Semerdjiev, Dimitrios Velenis
    Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1125-1128 [Conf]
    
11. William R. Roberts, Dimitrios Velenis
    Power supply variation effects on timing characteristics of clocked registers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
12. Itisha Chanodia, Dimitrios Velenis
    Effects of crosstalk noise on H-tree clock distribution networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
13. 
    On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking. [Citation Graph (, )][DBLP]
    
    
14. 
    Impact of 3D design choices on manufacturing cost. [Citation Graph (, )][DBLP]