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José Nelson Amaral: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Robert Niewiadomski, José Nelson Amaral, Robert C. Holte
    Sequential and Parallel Algorithms for Frontier A* with Delayed Duplicate Detection. [Citation Graph (0, 0)][DBLP]
    AAAI, 2006, pp:- [Conf]
  2. Christopher Barton, José Nelson Amaral, Bob Blainey
    Should potential loop optimizations influence inlining decisions? [Citation Graph (0, 0)][DBLP]
    CASCON, 2003, pp:30-38 [Conf]
  3. Christopher Barton, Peng Zhao, Robert Niewiadomski, José Nelson Amaral
    Identifying opportunities for automatic remote field cloning. [Citation Graph (0, 0)][DBLP]
    CASCON, 2004, pp:124-134 [Conf]
  4. Zhuang Guo, José Nelson Amaral, Duane Szafron, Yang Wang
    Utilizing field usage patterns for Java heap space optimization. [Citation Graph (0, 0)][DBLP]
    CASCON, 2006, pp:67-79 [Conf]
  5. Christopher Barton, Arie Tal, Bob Blainey, José Nelson Amaral
    Generalized Index-Set Splitting. [Citation Graph (0, 0)][DBLP]
    CC, 2005, pp:106-120 [Conf]
  6. Artour Stoutchinin, José Nelson Amaral, Guang R. Gao, James C. Dehnert, Suneel Jain, Alban Douillet
    Speculative Prefetching of Induction Pointers. [Citation Graph (0, 0)][DBLP]
    CC, 2001, pp:289-303 [Conf]
  7. Neil Birkbeck, Jonathan Levesque, José Nelson Amaral
    A Dimension Abstraction Approach to Vectorization in Matlab. [Citation Graph (0, 0)][DBLP]
    CGO, 2007, pp:115-130 [Conf]
  8. Paul Berube, José Nelson Amaral, Mike MacGregor
    An FPGA prototype for the experimental evaluation of a multizone network cache. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:253- [Conf]
  9. Paul Berube, Ashley Zinyk, José Nelson Amaral, Mike MacGregor
    The Bank Nth Chance Replacement Policy for FPGA-Based CAMs. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:648-660 [Conf]
  10. Robert Niewiadomski, José Nelson Amaral, Robert C. Holte
    Crafting Data Structures: A Study of Reference Locality in Refinement-Based Pathfinding. [Citation Graph (0, 0)][DBLP]
    HiPC, 2003, pp:438-448 [Conf]
  11. Robert Niewiadomski, José Nelson Amaral, Robert C. Holte
    A Parallel External-Memory Frontier Breadth-First Traversal Algorithm for Clusters of Workstations. [Citation Graph (0, 0)][DBLP]
    ICPP, 2006, pp:531-538 [Conf]
  12. Peng Zhao, José Nelson Amaral
    Feedback-Directed Switch-Case Statement Optimization. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2005, pp:295-302 [Conf]
  13. Gary M. Zoppetti, Gagan Agrawal, Lori L. Pollock, José Nelson Amaral, Xinan Tang, Guang R. Gao
    Automatic compiler techniques for thread coarsening for multithreaded architectures. [Citation Graph (0, 0)][DBLP]
    ICS, 2000, pp:306-315 [Conf]
  14. Ramaswamy Govindarajan, Hongbo Yang, Chihong Zhang, José Nelson Amaral, Guang R. Gao
    Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:26- [Conf]
  15. Wen-Yen Lin, Jean-Luc Gaudiot, José Nelson Amaral, Guang R. Gao
    Caching Single-Assignment Structures to Build a Robust Fine-Grain Multi-Threading System. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:589-594 [Conf]
  16. José Nelson Amaral, Guang R. Gao, Erturk Dogan Kocalar, Patrick O'Neill, Xinan Tang
    Design and Implementation of an Efficient Thread Partitioning Algorithm. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2000, pp:252-259 [Conf]
  17. Sean Ryan, José Nelson Amaral, Guang R. Gao, Zachary Ruiz, Andrés Márquez, Kevin B. Theobald
    Coping with very High Latencies in Petaflop Computer Systems. [Citation Graph (0, 0)][DBLP]
    ISHPC, 1999, pp:71-82 [Conf]
  18. Bob Blainey, Christopher Barton, José Nelson Amaral
    Removing Impediments to Loop Fusion Through Code Transformations. [Citation Graph (0, 0)][DBLP]
    LCPC, 2002, pp:309-328 [Conf]
  19. Alban Douillet, José Nelson Amaral, Guang R. Gao
    Fine-Grain Stacked Register Allocation for the Itanium Architecture. [Citation Graph (0, 0)][DBLP]
    LCPC, 2002, pp:344-361 [Conf]
  20. Peng Zhao, José Nelson Amaral
    To Inline or Not to Inline? Enhanced Inlining Decisions. [Citation Graph (0, 0)][DBLP]
    LCPC, 2003, pp:405-419 [Conf]
  21. Soraya Kasnavi, Paul Berube, Vincent C. Gaudet, José Nelson Amaral
    A Multizone Pipelined Cache for IP Routing. [Citation Graph (0, 0)][DBLP]
    NETWORKING, 2005, pp:574-585 [Conf]
  22. Charles Wallace, Guy Tremblay, José Nelson Amaral
    On the Tamability of the Location Consistency Memory Model. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2002, pp:1542-1550 [Conf]
  23. Christopher Barton, Calin Cascaval, George Almási, Yili Zheng, Montse Farreras, Siddhartha Chatterjee, José Nelson Amaral
    Shared memory programming for large scale machines. [Citation Graph (0, 0)][DBLP]
    PLDI, 2006, pp:108-117 [Conf]
  24. José Nelson Amaral, Wen-Yen Lin, Jean-Luc Gaudiot, Guang R. Gao
    Exploiting Locality in Single Assignment Data Structures Updated Through Split-Phase Transactions. [Citation Graph (0, 0)][DBLP]
    Cluster Computing, 2001, v:4, n:4, pp:281-293 [Journal]
  25. Guy Tremblay, C. J. Morrone, José Nelson Amaral, Guang R. Gao
    Implementation of the EARTH programming model on SMP clusters: a multi-threaded language and runtime system. [Citation Graph (0, 0)][DBLP]
    Concurrency and Computation: Practice and Experience, 2003, v:15, n:9, pp:821-844 [Journal]
  26. Robert Niewiadomski, José Nelson Amaral, Robert C. Holte
    A performance study of data layout techniques for improving data locality in refinement-based pathfinding. [Citation Graph (0, 0)][DBLP]
    ACM Journal of Experimental Algorithms, 2004, v:9, n:, pp:- [Journal]
  27. Charles Wallace, Guy Tremblay, José Nelson Amaral
    An Abstract State Machine Specification and Verification of the Location Consistency Memory Model and Cache Protocol. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2001, v:7, n:11, pp:1088-1112 [Journal]
  28. Angela French, José Nelson Amaral
    Eliminating Redundant Join-Set Computations in Static Single Assignment. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2006, v:12, n:8, pp:1007-1019 [Journal]
  29. Paras Mehta, José Nelson Amaral, Duane Szafron
    Is MPI suitable for a generative design-pattern system? [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2006, v:32, n:7-8, pp:616-626 [Journal]
  30. Prasad Kakulavarapu, Olivier Maquelin, José Nelson Amaral, Guang R. Gao
    Dynamic Load Balancers for a Multithreaded Multiprocessor System. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 2001, v:11, n:1, pp:169-184 [Journal]
  31. Ramaswamy Govindarajan, Hongbo Yang, José Nelson Amaral, Chihong Zhang, Guang R. Gao
    Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:1, pp:4-20 [Journal]
  32. Paul Berube, Mike MacGregor, José Nelson Amaral
    FPGA implementation and experimental evaluation of a multizone network cache. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:237-252 [Journal]
  33. Johnny Huynh, José Nelson Amaral, Paul Berube, Sid Ahmed Ali Touati
    Evaluation of Offset Assignment Heuristics. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:261-275 [Conf]
  34. Kevin Andrusky, Stephen Curial, José Nelson Amaral
    Tree-Traversal Orientation Analysis. [Citation Graph (0, 0)][DBLP]
    LCPC, 2006, pp:220-234 [Conf]
  35. Christopher Barton, Calin Cascaval, José Nelson Amaral
    A Characterization of Shared Data Access Patterns in UPC Programs. [Citation Graph (0, 0)][DBLP]
    LCPC, 2006, pp:111-125 [Conf]
  36. Timothy Furtak, José Nelson Amaral, Robert Niewiadomski
    Using SIMD registers and instructions to enable instruction-level parallelism in sorting algorithms. [Citation Graph (0, 0)][DBLP]
    SPAA, 2007, pp:348-357 [Conf]

  37. Compiling Python to a hybrid execution environment. [Citation Graph (, )][DBLP]


  38. Mining Opportunities for Code Improvement in a Just-In-Time Compiler. [Citation Graph (, )][DBLP]


  39. Workload Reduction for Multi-input Feedback-Directed Optimization. [Citation Graph (, )][DBLP]


  40. Topic 9: Parallel and Distributed Programming. [Citation Graph (, )][DBLP]


  41. The MAP3S Static-and-Regular Mesh Simulation and Wavefront Parallel-Programming Patterns. [Citation Graph (, )][DBLP]


  42. Mining for Paths in Flow Graphs. [Citation Graph (, )][DBLP]


  43. Aestimo: a feedback-directed optimization evaluation tool. [Citation Graph (, )][DBLP]


  44. MPADS: memory-pooling-assisted data splitting. [Citation Graph (, )][DBLP]


  45. Multidimensional Blocking in UPC. [Citation Graph (, )][DBLP]


  46. Using ZBDDs in Points-to Analysis. [Citation Graph (, )][DBLP]


  47. Function Outlining and Partial Inlining. [Citation Graph (, )][DBLP]


  48. A cache-based internet protocol address lookup architecture. [Citation Graph (, )][DBLP]


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