
Search the dblp DataBase
Jan Schier:
[Publications]
[Author Rank by year]
[Coauthors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
 Miroslav Lícko, Jan Schier, Milan Tichý, Markus Kühl
MATLAB/Simulink Based Methodology for RapidFPGAPrototyping. [Citation Graph (0, 0)][DBLP] FPL, 2003, pp:984987 [Conf]
 Jan Schier, Antonin Hermanek
Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA. [Citation Graph (0, 0)][DBLP] FPL, 2004, pp:11491151 [Conf]
 Zdenek Pohl, Jan Schier, Miroslav Lícko, Antonin Hermanek, Milan Tichý, Rudolf Matousek, Jiri Kadlec
Logarithmic Arithmetic for Real Data Types and Support for Matlab/Simulink Based RapidFPGAPrototyping. [Citation Graph (0, 0)][DBLP] IPDPS, 2003, pp:190 [Conf]
 Milan Tichý, Jan Schier, David Gregg
Efficient FloatingPoint Implementation of HighOrder (N)LMS Adaptive Filters in FPGA. [Citation Graph (0, 0)][DBLP] ARC, 2006, pp:311316 [Conf]
 Premysl Sucha, Zdenek Hanzálek, Antonin Hermanek, Jan Schier
Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design  Implementation of Finite Interval Constant Modulus Algorithm. [Citation Graph (0, 0)][DBLP] VLSI Signal Processing, 2007, v:46, n:1, pp:3553 [Journal]
FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic. [Citation Graph (, )][DBLP]
Search in 0.011secs, Finished in 0.012secs
