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Giovanni Fiorenza: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip Restle, Mary Yvonne Lanzerotti
    Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:38-43 [Conf]
  2. Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand
    Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:43-50 [Conf]
  3. Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand
    Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2005, v:49, n:4-5, pp:777-803 [Journal]
  4. Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David P. Conrady, Giovanni Fiorenza, I. Cevdet Noyan
    Estimating the efficiency of collaborative problem-solving, with applications to chip design. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2003, v:47, n:1, pp:77-88 [Journal]
  5. Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David P. Conrady, Daniel N. Maynard, Giovanni Fiorenza, I. Cevdet Noyan
    The physical design of on-chip interconnections. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:254-276 [Journal]
  6. Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand
    Assessment of on-chip wire-length distribution models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1108-1112 [Journal]
  7. Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand
    Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1330-1347 [Journal]
  8. Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand
    Impact of interconnect length changes on effective materials properties (dielectric constant). [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:73-80 [Conf]

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