Journals in DBLP

IEEE Trans. VLSI Syst.
2004, volume: 12, number: 10

1. Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska
   Individual wire-length prediction with application to timing-driven placement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1004-1014 [Journal]
   
2. Jason Helge Anderson, Farid N. Najm
   Power estimation techniques for FPGAs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1015-1027 [Journal]
   
3. Chao-Yang Yeh, Malgorzata Marek-Sadowska
   Sequential delay budgeting with interconnect prediction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1028-1037 [Journal]
   
4. André DeHon, Raphael Rubin
   Design of FPGA interconnect for multilevel metallization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1038-1050 [Journal]
   
5. André DeHon
   Unifying mesh- and tree-based programmable interconnect. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1051-1065 [Journal]
   
6. Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
   Empirical models for net-length probability distribution and applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1066-1075 [Journal]
   
7. Ketan N. Patel, Igor L. Markov
   Error-correction and crosstalk avoidance in DSM busses. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1076-1080 [Journal]
   
8. Payam Heydari, Ravindran Mohanavelu
   Design of ultrahigh-speed low-voltage CMOS CML buffers and latches. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1081-1093 [Journal]
   
9. Massimo Alioto, Gaetano Palumbo, Massimo Poli
   Evaluation of energy consumption in RC ladder circuits driven by a ramp input. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1094-1107 [Journal]
   
10. Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand
    Assessment of on-chip wire-length distribution models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1108-1112 [Journal]
    
11. R. H. Turner, R. F. Woods
    Highly efficient, limited range multipliers for LUT-based FPGA architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1113-1118 [Journal]
    
12. Stelian Alupoaei, Srinivas Katkoori
    Ant colony system application to macrocell overlap removal. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1118-1123 [Journal]
    
13. Tali Moreshet, R. Iris Bahar
    Effects of speculation on performance and issue queue design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1123-1126 [Journal]
    
14. M. Maymandi-Nejad, Manoj Sachdev
    Correction to "A Digitally Programmable Delay Element: Design and Analysis". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1126-1126 [Journal]