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José Alberto Espejo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
    Functional extension of structural logic optimization techniques. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:467-472 [Conf]
  2. José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
    Generalized reasoning scheme for redundancy addition and removal logic optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:391-397 [Conf]
  3. Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno
    Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:516-520 [Conf]
  4. Enrique San Millán, Luis Entrena, José Alberto Espejo
    On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:292-299 [Conf]
  5. José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
    Logic Restructuring for MUX-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1161-0 [Conf]
  6. Enrique San Millán, Luis Entrena, José Alberto Espejo
    On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:91-94 [Conf]
  7. Luis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo
    Logic Optimization of Unidirectional Circuits with Structural Methods. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:43-47 [Conf]
  8. Enrique San Millán, Luis Entrena, José Alberto Espejo, Celia López
    Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:529-541 [Journal]

  9. Logic Transformations by Multiple Wire Network Addition. [Citation Graph (, )][DBLP]


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