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Conferences in DBLP

Design, Automation, and Test in Europe (date)
1999 (conf/date/1999)


  1. Reuse of IP and virtual components. [Citation Graph (, )][DBLP]

  2. Jouko Junkkari
    Higher Product Complexity and Shorter Development Time - Continuous Challenge to Design and Test Environment. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:2-3 [Conf]
  3. Peter Thoma
    Automotive Electronics - A Challenge For Systems Engineering. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:4- [Conf]
  4. T. W. Williams
    Testing in Nanometer Technologies. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:5-0 [Conf]
  5. Gianpiero Cabodi, Paolo Camurati, Claudio Passerone, Stefano Quer
    Computing Timed Transition Relations for Sequential Cycle-Based Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:8-12 [Conf]
  6. Youpyo Hong, Peter A. Beerel
    Symbolic Reachability Analysis of Large Finite State Machines Using Don't Cares. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:13-0 [Conf]
  7. Enoch Hwang, Frank Vahid, Yu-Chin Hsu
    FSMD Functional Partitioning for Low Power. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:22-27 [Conf]
  8. Gerd Jochens, Lars Kruse, Eike Schmidt, Wolfgang Nebel
    A New Parameterizable Power Macro-Model for Datapath Components. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:29-0 [Conf]
  9. Annette Reutter, Wolfgang Rosenstiel
    An Efficient Reuse System for Digital Circuit Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:38-43 [Conf]
  10. Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura
    An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:44-0 [Conf]
  11. Stefan Höreth, Rolf Drechsler
    Formal Verification of Word-Level Specifications. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:52-57 [Conf]
  12. Hans Eveking, Holger Hinrichsen, Gerd Ritter
    Automatic Verification of Scheduling Results in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:59-64 [Conf]
  13. Michaela Huhn, Klaus Schneider, Thomas Kropf, George Logothetis
    Verifying Imprecisely Working Arithmetic Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:65-0 [Conf]
  14. Massoud Pedram, Qing Wu
    Battery-Powered Digital CMOS Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:72-76 [Conf]
  15. Eui-Young Chung, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
    Dynamic Power Management for non-stationary service requests. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:77-81 [Conf]
  16. Rajeev Murgai, Masahiro Fujita
    On Reducing Transitions Through Data Modifications. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:82-0 [Conf]
  17. Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh, Román Hermida, Milagros Fernández
    Kernel Scheduling in Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:90-96 [Conf]
  18. Bharat P. Dav
    CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:97-104 [Conf]
  19. Rainer Leupers
    Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:105-0 [Conf]
  20. Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas
    Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:112-116 [Conf]
  21. Antonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian
    An Effective BIST Architecture for Fast Multiplier Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:117-121 [Conf]
  22. Issam Alzaher-Noufal, Michael Nicolaidis
    A CAD Framework for Generating Self-Checking 1 Multipliers Based on Residue Codes. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:122-0 [Conf]
  23. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
    An Efficient Filter-Based Approach for Combinational Verification. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:132-137 [Conf]
  24. Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton
    Using Combinational Verification for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:138-144 [Conf]
  25. João P. Marques Silva, Thomas Glass
    Combinational Equivalence Checking Using Satisfiability and Recursive Learning. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:145-149 [Conf]
  26. Stefan Hendricx, Luc J. M. Claesen
    Formally Verified Redundancy Removal. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:150-0 [Conf]
  27. Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu
    Logic Transformation for Low Power Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:158-162 [Conf]
  28. Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Glitch Power Minimization by Gate Freezing. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:163-167 [Conf]
  29. Winfried Nöth, Reiner Kolla
    Spanning Tree-based State Encoding for Low Power Dissipation. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:168-174 [Conf]
  30. Michael S. Hsiao
    Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:175-0 [Conf]
  31. Érika F. Cota, Luigi Carro, Marcelo Lubaszewski
    A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:184-188 [Conf]
  32. Alfred V. Gomes, Abhijit Chatterjee
    Minimal Length Diagnostic Tests for Analog Circuits using Test History. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:189-194 [Conf]
  33. Sasikumar Cherubal, Abhijit Chatterjee
    Parametric Fault Diagnosis for Analog Systems Using Functional Mapping. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:195-0 [Conf]
  34. Meenakshi Kaul, Ranga Vemuri
    Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:202-209 [Conf]
  35. Christoph Jäschke, Rainer Laur, Friedrich Beckmann
    Time Constrained Modulo Scheduling with Global Resource Sharing. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:210-216 [Conf]
  36. James Smith, Giovanni De Micheli
    Polynomial Methods for Allocating Complex Components. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:217-222 [Conf]
  37. Nazanin Mansouri, Ranga Vemuri
    Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:223-0 [Conf]
  38. A. Lechner, J. Ferguson, A. Richardson, B. Hermes
    A Digital Partial Built-In Self-Test for a High Performance Automatic Gain Control Circuit . [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:232-238 [Conf]
  39. Laurent Latorre, Yves Bertrand, P. Hazard, F. Pressecq, Pascal Nouet
    Design, Characterization & Modelling of a CMOS Magnetic Field Sensor. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:239-243 [Conf]
  40. Zheng Rong Yang, Mark Zwolinski
    Fast, Robust DC and Transient Fault Simulation for Nonlinear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:244-248 [Conf]
  41. Franc Novak, Bojan Hvala, Sandi Klavzar
    On Analog Signature Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:249-0 [Conf]
  42. Axel Jantsch, Shashi Kumar, Ahmed Hemani
    The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:256-262 [Conf]
  43. Robert P. Dick, Niraj K. Jha
    MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:263-270 [Conf]
  44. Radim Cmar, Luc Rijnders, Patrick Schaumont, Serge Vernalde, Ivo Bolsens
    A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:271-0 [Conf]
  45. Joan Carletta, Mehrdad Nourani, Christos A. Papachristou
    Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:278-282 [Conf]
  46. Yiorgos Makris, Alex Orailoglu
    Channel-Based Behavioral Test Synthesis for Improved Module Reachability. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:283-288 [Conf]
  47. Nicola Nicolici, Bashir M. Al-Hashimi
    Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:289-0 [Conf]
  48. Katsuyuki Ochiai, Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura
    High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:303-308 [Conf]
  49. Bassam Tabbara, Marco Sgroi, Alberto L. Sangiovanni-Vincentelli, Enrica Filippi, Luciano Lavagno
    Fast Hardware-Software Co-simulation Using VHDL Models. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:309-0 [Conf]
  50. Chris J. M. Verhoeven, Arie van Staveren
    Systematic Biasing of Negative Feedback Amplifiers. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:318-322 [Conf]
  51. Robert Schwencker, Josef Eckmueller, Helmut E. Graeb, Kurt Antreich
    Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:323-327 [Conf]
  52. Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
    Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:328-0 [Conf]
  53. Alex Doboli, Ranga Vemuri
    A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:338-345 [Conf]
  54. Peter T. Breuer, Natividad Martínez Madrid, Jonathan P. Bowen, Robert B. France, Maria M. Larrondo-Petrie, Carlos Delgado Kloos
    Reasoning about VHDL and VHDL-AMS using Denotational Semantics. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:346-352 [Conf]
  55. Hisashi Sasaki
    A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:353-0 [Conf]
  56. Bernard Antaki, Yvon Savaria, Nanhan Xiong, Saman Adham
    Design For Testability Method for CML Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:360-367 [Conf]
  57. Michele Favalli, Cecilia Metra
    On the Design of Self-Checking Functional Units Based on Shannon Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:368-375 [Conf]
  58. Dirk Niggemeyer, M. Rüffer
    Parametric Built-In Self-Test of VLSI Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:376-0 [Conf]
  59. Giovanni De Micheli
    Hardware Synthesis from C/C++ Models. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:382-383 [Conf]
  60. Guido Arnout
    C for System Level Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:384-386 [Conf]
  61. Abhijit Ghosh, Joachim Kunkel, Stan Y. Liao
    Hardware Synthesis from C/C++. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:387-389 [Conf]
  62. Kazutoshi Wakabayashi
    C-based Synthesis Experiences with a Behavior Synthesizer, "Cyber". [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:390-0 [Conf]
  63. Joao Paulo Costa, L. Miguel Silveira, Mike Chou
    Efficient Techniques for Accurate Extraction and Modeling of Substrate Coupling in Mixed-Signal IC's. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:396-400 [Conf]
  64. Erik Lauwers, Georges G. E. Gielen
    A Power Estimation Model for High-Speed CMOS A/D Converters. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:401-405 [Conf]
  65. Adrián Núñez-Aldana, Ranga Vemuri
    An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:406-411 [Conf]
  66. Oscar Guerra, J. D. Rodríguez-García, E. Roca, Francisco V. Fernández, Ángel Rodríguez-Vázquez
    An Accurate Error Control Mechanism for Simplification Before Generation Algorihms. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:412-0 [Conf]
  67. Peter Feldmann, Sharad Kapur, David E. Long
    Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:418-417 [Conf]
  68. Gerhard Tröster
    Potentials of Chip-Package Co-Design for High-Speed Digital Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:423-422 [Conf]
  69. Piet Wambacq, Stéphane Donnay, Hocine Ziad, Marc Engels, Hugo De Man, Ivo Bolsens
    A Single-Package Solution for Wireless Transceivers. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:425-0 [Conf]
  70. Michael Nicolaidis, Yervant Zorian
    Scaling Deeper to Submicron: On-Line Testing to the Rescue. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:432-0 [Conf]
  71. Laurent Fournier, Yaron Arbetman, Moshe Levinger
    Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors Family. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:434-441 [Conf]
  72. Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto
    Symbolic Functional Vector Generation for VHDL Specifications. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:442-0 [Conf]
  73. Xiang-Dong Tan, C.-J. Richard Shi
    Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:448-453 [Conf]
  74. Raimund Ubar, Jaan Raik, Adam Morawiec
    Cycle-based Simulation with Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:454-458 [Conf]
  75. Markus Bühler, Matthias Papesch, K. Kapp, Utz G. Baitinger
    Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:459-0 [Conf]
  76. Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
    Full Scan Fault Coverage With Partial Scan. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:468-472 [Conf]
  77. Jongchul Shin, Hyunjin Kim, Sungho Kang
    At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:473-0 [Conf]
  78. Jianwen Zhu, Daniel Gajski
    OpenJ: An Extensible System Level Design Language. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:480-484 [Conf]
  79. Ashok Halambi, Peter Grun, V. Ganesh, Asheesh Khare, Nikil D. Dutt, Alexandru Nicolau
    EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:485-490 [Conf]
  80. Martin Radetzki, Ansgar Stammermann, Wolfram Putzke-Röming, Wolfgang Nebel
    Data Type Analysis for Hardware Synthesis from Object-Oriented Models. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:491-0 [Conf]
  81. Heiko Holzheuer
    How to use Knowledge in an Analysis Process. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:498-502 [Conf]
  82. Lluis Ribas, Jordi Carrabina
    Digital MOS Circuit Partitioning with Symbolic Modeling. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:503-508 [Conf]
  83. Juan A. Montiel-Nelson, Saeid Nooshabadi, V. de Armas, Roberto Sarmiento, Antonio Núñez
    High Speed GaAs Subsystem Design using Feed Through Logic. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:509-0 [Conf]
  84. Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno
    Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:516-520 [Conf]
  85. Manuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas
    An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:521-525 [Conf]
  86. Luís Guerra e Silva, Luis Miguel Silveira, João P. Marques Silva
    Algorithms for Solving Boolean Satisfiability in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:526-530 [Conf]
  87. Leon Stok, Andrew J. Sullivan, Mahesh A. Iyer
    Wavefront Technology Mapping. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:531-0 [Conf]
  88. Viera Stopjaková, Hans A. R. Manhaeve, M. Sidiropulos
    On-Chip Transient Current Monitor for Testing of Low Voltage CMOS IC. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:538-542 [Conf]
  89. Josep Rius, Joan Figueras
    Exploring the Combination of IDDQ and iDDt Testing: Energy Testing. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:543-548 [Conf]
  90. Marcelino B. Santos, João Paulo Teixeira
    Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:549-0 [Conf]
  91. Steven Vercauteren, Jan van der Steen, Diederik Verkest
    Combining Software Synthesis and Hardware/Software Interface Generation to Meet Hard Real-Time Constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:556-561 [Conf]
  92. Mattias O'Nils, Axel Jantsch
    Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol Specification. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:562-567 [Conf]
  93. Jui-Ming Chang, Massoud Pedram
    Codex-dp: Co-design of Communicating Systems Using Dynamic Programming. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:568-0 [Conf]
  94. A. Toulouse, David Bernard, Christian Landrault, Pascal Nouet
    Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:576-580 [Conf]
  95. Sudip Nag, Kamal Chaudhary
    Post-Placement Residual-Overlap Removal with Minimal Movement. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:581-586 [Conf]
  96. Helena Krupnova, Gabriele Saucier
    Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:587-0 [Conf]
  97. Samuel Norman Hamilton, Alex Orailoglu, Andre Hertwig
    Self Recovering Controller and Datapath Codesign. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:596-601 [Conf]
  98. C. A. J. van Eijk, E. T. A. F. Jacobs, Bart Mesman, Adwin H. Timmer
    Identification and Exploitation of Symmetries in DSP Algorithms. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:602-608 [Conf]
  99. Luiz C. V. dos Santos, Jochen A. G. Jess
    Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:609-0 [Conf]
  100. Ivo Bolsens, Wojtek Maly, Ludo Deferm, Jo Borel, Harry J. M. Veendrick
    Single Chip or Hybrid System Integration. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:616-0 [Conf]
  101. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:618-622 [Conf]
  102. A. J. van de Goor, J. de Neef
    Industrial Evaluation of DRAM Tests. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:623-630 [Conf]
  103. Spyros Tragoudas, Maria K. Michael
    ATPG Tools for Delay Faults at the Functional Level. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:631-0 [Conf]
  104. Priyank Kalla, Maciej J. Ciesielski
    Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:638-642 [Conf]
  105. Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
    Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:643-649 [Conf]
  106. Klaus Eckl, Christian Legl
    Retiming Sequential Circuits with Multiple Register Classes. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:650-0 [Conf]
  107. Lun Ye, Foong-Charn Chang, Peter Feldmann, Rakesh Chadha, Nagaraj Ns, Frank Cano
    Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:658-663 [Conf]
  108. Janet Meiling Wang, Qingjian Yu, Ernest S. Kuh
    Coupled Noise Estimation for Distributed RC Interconnect Model. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:664-668 [Conf]
  109. Bernard N. Sheehan
    Projective Convolution: RLC Model-Order Reduction Using the Impulse Response. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:669-0 [Conf]
  110. Margarida F. Jacome, Helvio P. Peixoto, Ander Royo, Juan Carlos López
    The Design Space Layer: Supporting Early Design Space Exploration for Core-Based Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:676-683 [Conf]
  111. Marcello Dalpasso, Alessandro Bogliolo, Luca Benini
    Specification and Validation of Distributed IP-Based Designs with JavaCAD. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:684-688 [Conf]
  112. Cristina Barna, Wolfgang Rosenstiel
    Object-Oriented Reuse Methodology for VHDL. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:689-0 [Conf]
  113. Ahmed Amine Jerraya, Rolf Ernst
    Multi-Language System Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:696-0 [Conf]
  114. Sybille Hellebrand, Hans-Joachim Wunderlich, Vyacheslav N. Yarmolik
    Symmetric Transparent BIST for RAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:702-707 [Conf]
  115. Kamran Zarrineh, Shambhu J. Upadhyaya
    On Programmable Memory Built-In Self Test Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:708-713 [Conf]
  116. Kanad Chakraborty, Anurag Gupta, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder
    A Physical Design Tool for Built-in Self-Repairable Static RAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:714-0 [Conf]

  117. Java, VHDL-AMS, ADA or C for System Level Specifications? [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:720- [Conf]
  118. Eduard Moser, Wolfgang Nebel
    Case Study: System Model of Crane and Embedded Control. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:721-0 [Conf]
  119. Jean-François Agaësse, Bernard Laurent
    Virtual Components Application and Customization. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:726-727 [Conf]
  120. Jürgen Haase
    Design Methodology for IP Providers. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:728-0 [Conf]
  121. Patrick Dewilde
    Large European Programs in Microelectronic System and Circuit Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:734-0 [Conf]
  122. Jaan Raik, Raimund Ubar
    Sequential Circuit Test Generation Using Decision Diagram Models. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:736-740 [Conf]
  123. M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor
    Illegal State Space Identification for Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:741-746 [Conf]
  124. Yanti Santoso, Matthew C. Merten, Elizabeth M. Rudnick, Miron Abramovici
    FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:747-0 [Conf]
  125. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
    Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:754-755 [Conf]
  126. Karsten Strehl, Lothar Thiele
    Interval Diagram Techniques for Symbolic Model Checking of Petri Nets. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:756-757 [Conf]
  127. Mitchell A. Thornton, J. P. Williams, Rolf Drechsler, Nicole Drechsler
    Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:758-759 [Conf]
  128. Christoph Meinel, Christian Stangier
    Increasing Efficiency of Symbolic Model Checking by Accelerating Dynamic Variable Reordering. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:760-761 [Conf]
  129. William Fornaciari, Donatella Sciuto, Cristina Silvano
    Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:762-763 [Conf]
  130. Karlheinz Weiß, Thorsten Steckstor, Wolfgang Rosenstiel
    Emulation of a Fast Reactive Embedded System using a Real Time Operating System. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:764-765 [Conf]
  131. J. A. Maestro, Daniel Mozos, Román Hermida
    The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:766-767 [Conf]
  132. Josef Fleischmann, Klaus Buchenrieder, Rainer Kress
    Codesign of Embedded Systems Based on Java and Reconfigurable Hardware Components. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:768-769 [Conf]
  133. A. Maamar, G. Russell
    ADOLT - An ADaptable On - Line Testing Scheme for VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:770-771 [Conf]
  134. Krzysztof Kuchcinski
    Integrated Resource Assignment and Scheduling of Task Graphs Using Finite Domain Constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:772-773 [Conf]
  135. Christos A. Papachristou, Yusuf Alzazeri
    A Method of Distributed Controller Design for RTL Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:774-775 [Conf]
  136. Jung Hyun Choi, Sergio Bampi
    OTA Amplifiers Design on Digital Sea-of-Transistors Array. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:776-777 [Conf]
  137. Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami
    A DAG-Based Design Approach for Reconfigurable VLIW Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:778-779 [Conf]
  138. Jue Wu, Gary S. Greenstein, Elizabeth M. Rudnick
    A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:780-781 [Conf]
  139. Olivier Pasquier, Jean Paul Calvez
    An Object-Based Executable Model for Simulation of Real-Time Hw/Sw Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:782-783 [Conf]
  140. Stefan Scherber, Christian Müller-Schloer
    An Efficient and Flexible Methodology for Modelling and Simulation of Heterogeneous Mechatronic Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:784-785 [Conf]
  141. Peter M. Maurer, William J. Schilp
    Software Bit-Slicing: A Technique for Improving Simulation Performance. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:786-787 [Conf]
  142. Françoise Martinolle, Charles Dawson, Debra Corlette, Mike Floyd
    Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:788-789 [Conf]
  143. Jerzy Dabrowski, Andrzej Pulka
    Experiences with Modeling of Analog and Mixed A/D Systems Based on PWL Technique. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:790-791 [Conf]
  144. Iyad Rayane, J. Velasco-Medina, Michael Nicolaidis
    A One-Bit-Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate Detection. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:792-0 [Conf]
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