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Mike W. T. Wong :
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K. Y. Ko , Mike W. T. Wong New built-in self-test technique based on addition/subtraction of selected node voltages. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2000, pp:39-0 [Conf ] K. Y. Ko , Mike W. T. Wong , Y. S. Lee Testing System-On-Chip by Summations of Cores? Test Output Voltages. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2002, pp:350-355 [Conf ] Joseph C. W. Pang , Mike W. T. Wong , Y. S. Lee Design and Implementation of Strongly Code-Disjoint CMOS Built-in Intermediate Voltage Sensor for Totally Self-Checking Circuits. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1997, pp:82-87 [Conf ] Tao Wei , Mike W. T. Wong , Y. S. Lee Efficient Multifrequency Analysis of Fault Diagnosis in Analog Circuits Based on Large Change Sensitivity Computation. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1996, pp:232-237 [Conf ] Mike W. T. Wong Issues Related to the Formulation of DFT Solution for Analog Circuit Test Using Equivalent Fault Analysis. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2003, pp:120-123 [Conf ] Mike W. T. Wong , Matthew Worsman DC Nonlinear Circuit Fault Simulation With Large Change Sensitivity. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1998, pp:366-371 [Conf ] Mike W. T. Wong , Yubin Zhang Design and Implementation of Self-Testable Full Range Window Comparator. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2004, pp:314-318 [Conf ] Matthew Worsman , Mike W. T. Wong , Y. S. Lee Analog circuit equivalent faults in the D.C. domain. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2000, pp:84-89 [Conf ] Mike W. T. Wong , K. Y. Ko , Y. S. Lee Analog and Mixed-Signal IP Cores Testing. [Citation Graph (0, 0)][DBLP ] DELTA, 2002, pp:3-7 [Conf ] Matthew Worsman , Mike W. T. Wong , Y. S. Lee Enhancing The Static D. C. Fault Diagnosis Of A Resistance Temperature Detector Sensor Circuit Using Equivalent Fault Analysis. [Citation Graph (0, 0)][DBLP ] DELTA, 2002, pp:443-446 [Conf ] Yingquan Zhou , Mike W. T. Wong , Yinghua Min Feasibility and Effectiveness of the Algorithm for Overhead Reduction in Analog Checkers. [Citation Graph (0, 0)][DBLP ] FTCS, 1995, pp:238-247 [Conf ] Matthew Worsman , Mike W. T. Wong , Y. S. Lee A Pre-Simulation Measure of D.C. Design-for-Testability Fault Diagnosis Quality. [Citation Graph (0, 0)][DBLP ] ISQED, 2000, pp:361-368 [Conf ] Search in 0.014secs, Finished in 0.015secs