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Derek Chiou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Boon Seong Ang, Derek Chiou, Larry Rudolph, Arvind
    The StarT-Voyager Parallel System. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:185-0 [Conf]
  2. Derek Chiou, Prabhat Jain, Larry Rudolph, Srinivas Devadas
    Application-specific memory management for embedded systems using software-controlled caches. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:416-419 [Conf]
  3. Derek Chiou, Boon Seong Ang, Robert Greiner, Arvind, James C. Hoe, Michael J. Beckerle, James E. Hicks, G. Andrew Boughton
    START-NG: Delivering Seamless Parallel Computing. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1995, pp:101-116 [Conf]
  4. Boon Seong Ang, Derek Chiou, Larry Rudolph, Arvind
    Micro-Architectures of High Performance, Multi-User System Area Network Interface Cards. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:13-20 [Conf]
  5. Itamar Elhanany, Kurt Busch, Derek Chiou
    Switch Fabric Interfaces. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:9, pp:106-108 [Journal]
  6. James E. Hicks, Derek Chiou, Boon Seong Ang, Arvind
    Performance Studies of Id on the Monsoon Dataflow System. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1993, v:18, n:3, pp:273-300 [Journal]
  7. Venkat Natarajan, Derek Chiou, Boon Seong Ang
    Performance Visualization on Monsoon. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1993, v:18, n:2, pp:169-180 [Journal]
  8. Itamar Elhanany, Derek Chiou, Vahid Tabatabaee, Raffaele Noro, Ali Poursepanj
    The Network Processing Forum switch fabric benchmark specifications: an overview. [Citation Graph (0, 0)][DBLP]
    IEEE Network, 2005, v:19, n:2, pp:5-9 [Journal]
  9. John Wawrzynek, David Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic
    RAMP: Research Accelerator for Multiple Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:2, pp:46-57 [Journal]

  10. Soft connections: addressing the hardware-design modularity problem. [Citation Graph (, )][DBLP]

  11. The FAST methodology for high-speed SoC/computer simulation. [Citation Graph (, )][DBLP]

  12. Parallelizing computer system simulators. [Citation Graph (, )][DBLP]

  13. QUICK: A flexible full-system functional model. [Citation Graph (, )][DBLP]

  14. FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators. [Citation Graph (, )][DBLP]

  15. Early Models for System-Level Power Estimation. [Citation Graph (, )][DBLP]

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