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Publications of Author

1. Ramon Canal, Joan-Manuel Parcerisa, Antonio González
   A Cost-Effective Clustered Architecture. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 1999, pp:160-168 [Conf]
   
2. Ramon Canal, Antonio González, James E. Smith
   Software-Controlled Operand-Gating. [Citation Graph (0, 0)][DBLP]
   CGO, 2004, pp:125-136 [Conf]
   
3. Ramon Canal, Antonio González, James E. Smith
   Value Compression for Efficient Computation. [Citation Graph (0, 0)][DBLP]
   Euro-Par, 2005, pp:519-529 [Conf]
   
4. Ramon Canal, Joan-Manuel Parcerisa, Antonio González
   Dynamic Cluster Assignment Mechanisms. [Citation Graph (0, 0)][DBLP]
   HPCA, 2000, pp:133-0 [Conf]
   
5. Ramon Canal, Antonio González
   A low-complexity issue logic. [Citation Graph (0, 0)][DBLP]
   ICS, 2000, pp:327-335 [Conf]
   
6. Ramon Canal, Antonio González
   Reducing the complexity of the issue logic. [Citation Graph (0, 0)][DBLP]
   ICS, 2001, pp:312-320 [Conf]
   
7. Matteo Monchiero, Ramon Canal, Antonio González
   Design space exploration for multicore architectures: a power/performance/thermal view. [Citation Graph (0, 0)][DBLP]
   ICS, 2006, pp:177-186 [Conf]
   
8. Ramon Canal, Antonio González, James E. Smith
   Very low power pipelines using significance compression. [Citation Graph (0, 0)][DBLP]
   MICRO, 2000, pp:181-190 [Conf]
   
9. Ramon Canal, Joan-Manuel Parcerisa, Antonio González
   Dynamic Code Partitioning for Clustered Architectures. [Citation Graph (0, 0)][DBLP]
   International Journal of Parallel Programming, 2001, v:29, n:1, pp:59-79 [Journal]
   
10. Jaume Abella, Ramon Canal, Antonio González
    Power- and Complexity-Aware Issue Queue Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:5, pp:50-58 [Journal]
    
11. 
    Distributed cooperative caching. [Citation Graph (, )][DBLP]
    
    
12. 
    Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability. [Citation Graph (, )][DBLP]
    
    
13. 
    Power-Efficient Spilling Techniques for Chip Multiprocessors. [Citation Graph (, )][DBLP]
    
    
14. 
    Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs. [Citation Graph (, )][DBLP]
    
    
15. 
    Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors. [Citation Graph (, )][DBLP]
    
    
16. 
    MODEST: a model for energy estimation under spatio-temporal variability. [Citation Graph (, )][DBLP]
    
    
17. 
    Process Variation Tolerant 3T1D-Based Cache Architectures. [Citation Graph (, )][DBLP]
    
    
18. 
    An hybrid eDRAM/SRAM macrocell to implement first-level data caches. [Citation Graph (, )][DBLP]