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Matteo Monchiero: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
    Power/performance hardware optimization for synchronization intensive applications in MPSoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:606-611 [Conf]
  2. Oreste Villa, Patrick Schaumont, Ingrid Verbauwhede, Matteo Monchiero, Gianluca Palermo
    Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:804-805 [Conf]
  3. Matteo Monchiero, Gianluca Palermo
    The Combined Perceptron Branch Predictor. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2005, pp:487-496 [Conf]
  4. Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:440-443 [Conf]
  5. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    A design kit for a fully working shared memory multiprocessor on FPGA. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:219-222 [Conf]
  6. Matteo Monchiero, Ramon Canal, Antonio González
    Design space exploration for multicore architectures: a power/performance/thermal view. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:177-186 [Conf]
  7. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:331-336 [Conf]
  8. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:449-450 [Conf]
  9. Guido Bertoni, Vittorio Zaccaria, Luca Breveglieri, Matteo Monchiero, Gianluca Palermo
    AES Power Attack Based on Induced Cache Miss and Countermeasure. [Citation Graph (0, 0)][DBLP]
    ITCC (1), 2005, pp:586-591 [Conf]
  10. Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:515-524 [Journal]
  11. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
    Efficient Synchronization for Embedded On-Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:10, pp:1049-1062 [Journal]
  12. Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo
    Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:107-114 [Conf]
  13. Antonino Tumeo, Marco Branca, Lorenzo Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    An Interrupt Controller for FPGA-based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:82-87 [Conf]
  14. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
    Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:144-151 [Conf]
  15. Oreste Villa, Patrick Schaumont, Ingrid Verbauwhede, Matteo Monchiero, Gianluca Palermo
    Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  16. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
    Exploration of distributed shared memory architectures for NoC-based multiprocessors. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:10, pp:719-732 [Journal]

  17. A Self-Reconfigurable Implementation of the JPEG Encoder. [Citation Graph (, )][DBLP]


  18. Lightweight DMA management mechanisms for multiprocessors on FPGA. [Citation Graph (, )][DBLP]


  19. Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform. [Citation Graph (, )][DBLP]


  20. A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications. [Citation Graph (, )][DBLP]


  21. A Modular Approach to Model Heterogeneous MPSoC at Cycle Level. [Citation Graph (, )][DBLP]


  22. Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs. [Citation Graph (, )][DBLP]


  23. A multiprocessor self-reconfigurable JPEG2000 encoder. [Citation Graph (, )][DBLP]


  24. Corona: System Implications of Emerging Nanophotonic Technology. [Citation Graph (, )][DBLP]


  25. A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies. [Citation Graph (, )][DBLP]


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