Conferences in DBLP
Chi-Keung Luk , Robert Muth , Harish Patil , Robert S. Cohn , P. Geoffrey Lowney Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Dongkeun Kim , Shih-wei Liao , Perry H. Wang , Juan del Cuvillo , Xinmin Tian , Xiang Zou , Hong Wang , Donald Yeung , Milind Girkar , John Paul Shen Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Antonia Zhai , Christopher B. Colohan , J. Gregory Steffan , Todd C. Mowry Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Dupré , Nathalie Drach , Olivier Temam VHC: Quickly Building an Optimizer for Complex Embedded Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Sungdo Moon , Xinliang D. Li , Robert Hundt , Dhruva R. Chakrabarti , Luis A. Lozano , Uma Srinivasan , Shin-Ming Liu SYZYGY - A Framework for Scalable Cross-Module IPO. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Lattner , Vikram S. Adve LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] Kim M. Hazelwood , James E. Smith Exploring Code Cache Eviction Granularities in Dynamic Optimization Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ali-Reza Adl-Tabatabai , Jay Bharadwaj , Michal Cierniak , Marsha Eng , Jesse Fang , Brian T. Lewis , Brian R. Murphy , James M. Stichnoth Improving 64-Bit Java IPF Performance by Compressing Heap References. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoming Li , María Jesús Garzarán , David A. Padua A Dynamically Tuned Sorting Library. [Citation Graph (0, 0)][DBLP ] Conf ] Ramon Canal , Antonio González , James E. Smith Software-Controlled Operand-Gating. [Citation Graph (0, 0)][DBLP ] Conf ] Yoav Almog , Roni Rosner , Naftali Schwartz , Ari Schmorak Specialized Dynamic Optimizations for High-Performance Energy-Efficient Microarchitecture. [Citation Graph (0, 0)][DBLP ] Conf ] Mikhail Smelyanskiy , Scott A. Mahlke , Edward S. Davidson Probabilistic Predicate-Aware Modulo Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Hongbo Rong , Zhizhong Tang , Ramaswamy Govindarajan , Alban Douillet , Guang R. Gao Single-Dimension Software Pipelining for Multi-Dimensional Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Hongbo Rong , Alban Douillet , Ramaswamy Govindarajan , Guang R. Gao Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Sebastian Winkel Exploring the Performance Potential of Itanium® Processors with ILP-based Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Manjunath Kudlur , Kevin Fan , Michael L. Chu , Rajiv A. Ravindran , Nathan Clark , Scott A. Mahlke FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Shiliang Hu , James E. Smith Using Dynamic Binary Translation to Fuse Dependent Instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Youfeng Wu , Mauricio Breternitz Jr. , Justin Quek , Orna Etzion , Jesse Fang The Accuracy of Initial Prediction in Two-Phase Dynamic Binary Translators. [Citation Graph (0, 0)][DBLP ] Conf ] Rahul Joshi , Michael D. Bond , Craig B. Zilles Targeted Path Profiling: Lower Overhead Path Profiling for Staged Dynamic Optimization Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sriraman Tallam , Xiangyu Zhang , Rajiv Gupta Extending Path Profiling across Loop Backedges and Procedure Boundaries. [Citation Graph (0, 0)][DBLP ] Conf ] Fabrice Rastello , François de Ferrière , Christophe Guillon Optimizing Translation Out of SSA Using Renaming Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Yonghua Ding , Zhiyuan Li A Compiler Scheme for Reusing Intermediate Computation Results. [Citation Graph (0, 0)][DBLP ] Conf ] Byoungro So , Mary W. Hall , Heidi E. Ziegler Custom Data Layout for Memory Parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Vlad-Mihai Panait , Amit Sasturkar , Weng-Fai Wong Static Identification of Delinquent Loads. [Citation Graph (0, 0)][DBLP ] Conf ] Qiang Wu , Artem Pyatakov , Alexey Spiridonov , Easwaran Raman , Douglas W. Clark , David I. August Exposing Memory Access Regularities Using Object-Relative Memory Profiling. [Citation Graph (0, 0)][DBLP ] Conf ] 