The SCEAS System
Navigation Menu

Search the dblp DataBase


Paulo Centoducatte: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Marcio Buss, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo
    Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures. [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:141-148 [Conf]
  2. Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo
    Multi-profile based code compression. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:244-249 [Conf]
  3. Paulo Centoducatte, Ricardo Pannain, Guido Araujo
    Compressed Code Execution on DSP Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:56-63 [Conf]
  4. Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel C. Casarotto, Luiz C. V. dos Santos, Max R. de O. Schultz, Olinto Furtado
    Automatic Retargeting of Binary Utilities for Embedded Code Generation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:253-258 [Conf]
  5. Guido Araujo, Paulo Centoducatte, Mario Cartes, Ricardo Pannain
    Code Compression Based on Operand Factorization. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:194-201 [Conf]
  6. Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo
    Multi-Profile Instruction Based Compression. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2004, pp:23-29 [Conf]
  7. Richard E. Billo, Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, Eduardo Wanderley Netto
    Design of a decompressor engine on a SPARC processor. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:110-114 [Conf]
  8. Fernando Kronbauer, Alexandro Baldassin, Bruno Albertini, Paulo Centoducatte, Sandro Rigo, Guido Araujo, Rodolfo Azevedo
    A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:123-129 [Conf]
  9. Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo, Ricardo Pannain
    Expression-tree-based algorithms for code compression on embedded RISC architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:530-533 [Journal]

  10. STM versus lock-based systems: an energy consumption perspective. [Citation Graph (, )][DBLP]

  11. Extending the ArchC Language for Automatic Generation of Assemblers. [Citation Graph (, )][DBLP]

  12. A Software Transactional Memory System for an Asymmetric Processor Architecture. [Citation Graph (, )][DBLP]

  13. SPARC16: A New Compression Approach for the SPARC Architecture. [Citation Graph (, )][DBLP]

  14. On the energy-efficiency of software transactional memory. [Citation Graph (, )][DBLP]

Search in 0.003secs, Finished in 0.004secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002