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Publications of Author

1. Mahmut T. Kandemir, Ismail Kadayif, Alok N. Choudhary, Joseph Zambreno
   Optimizing inter-nest data locality. [Citation Graph (0, 0)][DBLP]
   CASES, 2002, pp:127-135 [Conf]
   
2. Joseph Zambreno, Alok N. Choudhary, Rahul Simha, Bhagirath Narahari
   Flexible Software Protection Using Hardware/Software Codesign Techniques. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:636-641 [Conf]
   
3. Joseph Zambreno, Mahmut T. Kandemir, Alok N. Choudhary
   Enhancing Compiler Techniques for Memory Energy Optimizations. [Citation Graph (0, 0)][DBLP]
   EMSOFT, 2002, pp:364-381 [Conf]
   
4. Joseph Zambreno, Dan Honbo, Alok N. Choudhary
   Exploiting Multi-Grained Parallelism in Reconfigurable SBC Architectures. [Citation Graph (0, 0)][DBLP]
   FCCM, 2005, pp:333-334 [Conf]
   
5. Joseph Zambreno, Rahul Simha, Alok N. Choudhary
   Addressing application integrity attacks using a reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
   FPGA, 2004, pp:250- [Conf]
   
6. David Nguyen, Joseph Zambreno, Gokhan Memik
   Flow Monitoring in High-Speed Networks with 2D Hash Tables. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:1093-1097 [Conf]
   
7. Joseph Zambreno
   Design and Evaluation of an FPGA Architecture for Software Protection. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:1180- [Conf]
   
8. Joseph Zambreno, David Nguyen, Alok N. Choudhary
   Exploring Area/Delay Tradeoffs in an AES FPGA Implementation. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:575-585 [Conf]
   
9. Olga Gelbart, Paul Ott, Bhagirath Narahari, Rahul Simha, Alok N. Choudhary, Joseph Zambreno
   CODESSEAL: Compiler/FPGA Approach to Secure Applications. [Citation Graph (0, 0)][DBLP]
   ISI, 2005, pp:530-535 [Conf]
   
10. Kripashankar Mohan, Bhagirath Narahari, Rahul Simha, Paul Ott, Alok N. Choudhary, Joseph Zambreno
    Performance Study of a Compiler/Hardware Approach to Embedded Systems Security. [Citation Graph (0, 0)][DBLP]
    ISI, 2005, pp:543-548 [Conf]
    
11. Joseph Zambreno, Alok N. Choudhary, Rahul Simha, Bhagirath Narahari, Nasir D. Memon
    SAFE-OPS: An approach to embedded software security. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:1, pp:189-210 [Journal]
    
12. Ramanathan Narayanan, Daniel Honbo, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno
    Interactive presentation: An FPGA implementation of decision tree classification. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:189-194 [Conf]
    
13. Ramanathan Narayanan, Berkin Özisikyilmaz, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno
    Quantization Error and Accuracy-Performance Tradeoffs for Embedded Data Mining Workloads. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science (3), 2007, pp:734-741 [Conf]
    
14. Ramanathan Narayanan, Berkin Özisikyilmaz, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary
    MineBench: A Benchmark Suite for Data Mining Workloads. [Citation Graph (0, 0)][DBLP]
    IISWC, 2006, pp:182-188 [Conf]
    
15. Berkin Özisikyilmaz, Ramanathan Narayanan, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary
    An Architectural Characterization Study of Data Mining and Bioinformatics Workloads. [Citation Graph (0, 0)][DBLP]
    IISWC, 2006, pp:61-70 [Conf]
    
16. 
    An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System. [Citation Graph (, )][DBLP]
    
    
17. 
    Detecting/preventing information leakage on the memory bus due to malicious hardware. [Citation Graph (, )][DBLP]
    
    
18. 
    Polymorphic wavelet architectures using reconfigurable hardware. [Citation Graph (, )][DBLP]
    
    
19. 
    Mining Association Rules with systolic trees. [Citation Graph (, )][DBLP]
    
    
20. 
    Evaluating the effects of cache redundancy on profit. [Citation Graph (, )][DBLP]
    
    
21. 
    A Reconfigurable Architecture for Secure Multimedia Delivery. [Citation Graph (, )][DBLP]
    
    
22. 
    Architectural Support for Automated Software Attack Detection, Recovery, and Prevention. [Citation Graph (, )][DBLP]
    
    
23. 
    Efficient Translation of Algorithmic Kernels on Large-Scale Multi-cores. [Citation Graph (, )][DBLP]
    
    
24. 
    Hardware Containers for Software Components: A Trusted Platform for COTS-Based Systems. [Citation Graph (, )][DBLP]
    
    
25. 
    Design and analysis of efficient reconfigurable wavelet filters. [Citation Graph (, )][DBLP]
    
    
26. 
    Experiments in attacking FPGA-based embedded systems using differential power analysis. [Citation Graph (, )][DBLP]
    
    
27. 
    A Reconfigurable Platform for Frequent Pattern Mining. [Citation Graph (, )][DBLP]
    
    
28. 
    Microarchitectures for Managing Chip Revenues under Process Variations. [Citation Graph (, )][DBLP]
    
    
29. 
    Providing secure execution environments with a last line of defense against Trojan circuit attacks. [Citation Graph (, )][DBLP]
    
    
30. 
    Preventing IC Piracy Using Reconfigurable Logic Barriers. [Citation Graph (, )][DBLP]