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Jingling Xue: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lian Li 0002, Lin Gao 0002, Jingling Xue
    Memory Coloring: A Compiler Approach for Scratchpad Memory Management. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2005, pp:329-338 [Conf]
  2. Lian Li 0002, Jingling Xue
    Trace-Based Data Cache Leakage Reduction at Link Time. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:175-188 [Conf]
  3. Canqun Yang, Xuejun Yang, Jingling Xue
    Improving the Performance of GCC by Exploiting IA-64 Architectural Features. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:236-251 [Conf]
  4. Phung Hua Nguyen, Jingling Xue
    Strength Reduction for Loop-Invariant Types. [Citation Graph (0, 0)][DBLP]
    ACSC, 2004, pp:213-222 [Conf]
  5. Phung Hua Nguyen, Jingling Xue
    Interprocedural Side-Effect Analysis and Optimisation in the Presence of Dynamic Class Loading. [Citation Graph (0, 0)][DBLP]
    ACSC, 2005, pp:9-18 [Conf]
  6. Budi Kurniawan, Jingling Xue
    A Comparative Study of Web Application Design Models Using the Java Technologies. [Citation Graph (0, 0)][DBLP]
    APWeb, 2004, pp:711-721 [Conf]
  7. Bernhard Scholz, Bernd Burgstaller, Jingling Xue
    Minimizing bank selection instructions for partitioned memory architecture. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:201-211 [Conf]
  8. Qiong Cai, Lin Gao 0002, Jingling Xue
    Region-Based Partial Dead Code Elimination on Predicated Code. [Citation Graph (0, 0)][DBLP]
    CC, 2004, pp:150-166 [Conf]
  9. Jingling Xue, Jens Knoop
    A Fresh Look at PRE as a Maximum Flow Problem. [Citation Graph (0, 0)][DBLP]
    CC, 2006, pp:139-154 [Conf]
  10. Jingling Xue, Phung Hua Nguyen
    Completeness Analysis for Incomplete Object-Oriented Programs. [Citation Graph (0, 0)][DBLP]
    CC, 2005, pp:271-286 [Conf]
  11. Jingling Xue, Christian Lengauer
    Specifying control signals for one-dimensional systolic arrays by uniform recurrence equations. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:181-186 [Conf]
  12. Qiong Cai, Jingling Xue
    Optimal and Efficient Speculation-Based Partial Redundancy Elimination. [Citation Graph (0, 0)][DBLP]
    CGO, 2003, pp:91-104 [Conf]
  13. Jingling Xue
    On the Loading, Recovery and Access of Stationary Data in Systolic Arrays. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1992, pp:259-264 [Conf]
  14. Xavier Vera, Jingling Xue
    Let's Study Whole-Program Cache Behaviour Analytically. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:175-186 [Conf]
  15. Jingling Xue
    Compiler-Directed Scratchpad Memory Management. [Citation Graph (0, 0)][DBLP]
    ICESS, 2005, pp:2- [Conf]
  16. Jingling Xue, Patrick M. Lenders
    Avoiding Data Link and Computational Conflicts in Mapping Nested Loop Algorithms to Lower-Dimensional Processor Arrays. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1994, pp:567-572 [Conf]
  17. Qingguang Huang, Jingling Xue, Xavier Vera
    Code Tiling for Improving the Cache Performance of PDE Solvers. [Citation Graph (0, 0)][DBLP]
    ICPP, 2003, pp:615-0 [Conf]
  18. Jingling Xue, Qingguang Huang, Minyi Guo
    Enabling Loop Fusion and Tiling for Cache Performance by Fixing Fusion-Preventing Data Dependences. [Citation Graph (0, 0)][DBLP]
    ICPP, 2005, pp:107-115 [Conf]
  19. Baoliu Ye, Minyi Guo, Jingling Xue
    CoopStream: A Cooperative Cache Based Streaming Schedule Scheme for On-demand Media Services on Overlay Networks. [Citation Graph (0, 0)][DBLP]
    ICPP, 2006, pp:577-584 [Conf]
  20. Jingling Xue
    Constructing DO loops for non-convex iteration spaces in compiling for parallel machines. [Citation Graph (0, 0)][DBLP]
    IPPS, 1995, pp:364-368 [Conf]
  21. Jingling Xue
    Affine-by-Statement Transformations of Imperfectly Nested Loops. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:34-38 [Conf]
  22. Jingling Xue
    Aggressive Loop Fusion for Improving Locality and Parallelism. [Citation Graph (0, 0)][DBLP]
    ISPA, 2005, pp:224-238 [Conf]
  23. Jingling Xue
    Communication-Minimal Tiling of Uniform Dependence Loops. [Citation Graph (0, 0)][DBLP]
    LCPC, 1996, pp:330-349 [Conf]
  24. Jingling Xue, Chua-Huang Huang
    Reuse-Driven Tiling for Data Locality. [Citation Graph (0, 0)][DBLP]
    LCPC, 1997, pp:16-33 [Conf]
  25. Lian Li 0002, Jingling Xue
    A trace-based binary compilation framework for energy-aware computing. [Citation Graph (0, 0)][DBLP]
    LCTES, 2004, pp:95-106 [Conf]
  26. Hui Wu, Joxan Jaffar, Jingling Xue
    Instruction Scheduling with Release Times and Deadlines on ILP Processors. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2006, pp:51-60 [Conf]
  27. Xavier Vera, Björn Lisper, Jingling Xue
    Data Caches in Multitasking Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    RTSS, 2003, pp:154-165 [Conf]
  28. Xavier Vera, Björn Lisper, Jingling Xue
    Data cache locking for higher program predictability. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2003, pp:272-282 [Conf]
  29. Jingling Xue
    An Algorithm to Automate Non-Unimodular Transformations of Loop Nests. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:512-521 [Conf]
  30. Weng-Long Chang, Michael (Shan-Hui) Ho, Minyi Guo, Xiaohong Jiang, Jingling Xue, Minglu Li
    Fast Parallel DNA-Based Algorithms for Molecular Computation: Determining a Prime Number. [Citation Graph (0, 0)][DBLP]
    ICITA (1), 2005, pp:447-452 [Conf]
  31. Jingling Xue, Xian-Long Hong
    A new data structure for representing cell hierarchy in layout design. [Citation Graph (0, 0)][DBLP]
    Computers & Graphics, 1988, v:12, n:3-4, pp:341-348 [Journal]
  32. Shiping Chen, Jingling Xue
    Partitioning and scheduling loops on NOWs. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 1999, v:22, n:11, pp:1017-1033 [Journal]
  33. Jingling Xue, Patrick M. Lenders
    Space-Time Equations for Non-Unimodular Mappings. [Citation Graph (0, 0)][DBLP]
    Int. J. Comput. Math., 2002, v:79, n:5, pp:555- [Journal]
  34. Jingling Xue, Chua-Huang Huang
    Reuse-Driven Tiling for Improving Data Locality. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1998, v:26, n:6, pp:671-696 [Journal]
  35. Pen-Chung Yew, Jingling Xue
    Forword. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:5, pp:575-576 [Journal]
  36. Jingling Xue
    Communication-Minimal Tiling of Uniform Dependence Loops. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1997, v:42, n:1, pp:42-59 [Journal]
  37. Lian Li 0002, Jingling Xue
    Trace-based leakage energy optimisations at link time. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:1, pp:1-20 [Journal]
  38. Jingling Xue, Phung Hua Nguyen, John Potter
    Interprocedural side-effect analysis for incomplete object-oriented software modules. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 2007, v:80, n:1, pp:92-105 [Journal]
  39. Patrick M. Lenders, Jingling Xue
    Eigenvectors-based parallelisation of nested loops with affine dependences. [Citation Graph (0, 0)][DBLP]
    Parallel Algorithms Appl., 2002, v:17, n:3, pp:227-248 [Journal]
  40. Jingling Xue
    Automating Non-Unimodular Loop Transformations for Massive Parallelism. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1994, v:20, n:5, pp:711-728 [Journal]
  41. Jingling Xue
    Transformations of Nested Loops with Non-Convex Iteration Spaces. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1996, v:22, n:3, pp:339-368 [Journal]
  42. Jingling Xue
    Unimodular Transformations of Non-Perfectly Nested Loops. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1997, v:22, n:12, pp:1621-1645 [Journal]
  43. Peiyi Tang, Jingling Xue
    Generating efficient tiled code for distributed memory machines. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2000, v:26, n:11, pp:1369-1410 [Journal]
  44. Jingling Xue, Wentong Cai
    Time-minimal tiling when rise is larger than zero. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2002, v:28, n:6, pp:915-939 [Journal]
  45. Jingling Xue
    Specifying control signals for Systolic Arrays by Uniform Recurrence Equations. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1991, v:1, n:, pp:83-93 [Journal]
  46. Jingling Xue
    On Tiling as a Loop Transformation. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1997, v:7, n:4, pp:409-424 [Journal]
  47. Jingling Xue, Qiong Cai, Lin Gao 0002
    Partial dead code elimination on predicated code regions. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 2006, v:36, n:15, pp:1655-1685 [Journal]
  48. Jingling Xue, Qiong Cai
    A lifetime optimal algorithm for speculative PRE. [Citation Graph (0, 0)][DBLP]
    TACO, 2006, v:3, n:2, pp:115-155 [Journal]
  49. Jingling Xue, Xavier Vera
    Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:5, pp:547-566 [Journal]
  50. Lian Li 0002, Hui Wu, Hui Feng, Jingling Xue
    Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2007, pp:63-74 [Conf]
  51. Yi Lu 0003, John Potter, Jingling Xue
    Validity Invariants and Effects. [Citation Graph (0, 0)][DBLP]
    ECOOP, 2007, pp:202-226 [Conf]
  52. Lei Pan, Jingling Xue, Ming Kin Lai, Michael B. Dillencourt, Lubomir F. Bic
    Toward Automatic Data Distribution for Migrating Computations. [Citation Graph (0, 0)][DBLP]
    ICPP, 2007, pp:27- [Conf]
  53. Lian Li 0002, Quan Hoang Nguyen, Jingling Xue
    Scratchpad allocation for data aggregates in superperfect graphs. [Citation Graph (0, 0)][DBLP]
    LCTES, 2007, pp:207-216 [Conf]

  54. Exploiting loop-dependent stream reuse for stream processors. [Citation Graph (, )][DBLP]


  55. Ownership Downgrading for Ownership Types. [Citation Graph (, )][DBLP]


  56. Optimal loop parallelization for maximizing iteration-level parallelism. [Citation Graph (, )][DBLP]


  57. Exploiting Speculative TLP in Recursive Programs by Dynamic Thread Prediction. [Citation Graph (, )][DBLP]


  58. Level by level: making flow- and context-sensitive pointer analysis scalable for millions of lines of code. [Citation Graph (, )][DBLP]


  59. Reuse-aware modulo scheduling for stream processors. [Citation Graph (, )][DBLP]


  60. Hardware Support for Efficient Sparse Matrix Vector Multiplication. [Citation Graph (, )][DBLP]


  61. Loop recreation for thread-level speculation. [Citation Graph (, )][DBLP]


  62. Thread-Sensitive Modulo Scheduling for Multicore Processors. [Citation Graph (, )][DBLP]


  63. Optimizing scientific application loops on stream processors. [Citation Graph (, )][DBLP]


  64. Software-Hardware Cooperative DRAM Bank Partitioning for Chip Multiprocessors. [Citation Graph (, )][DBLP]


  65. Comparability graph coloring for optimizing utilization of stream register files in stream processors. [Citation Graph (, )][DBLP]


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