Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1991, volume: 10, number: 12

1. Srinivas Devadas
   Optimizing interacting finite state machines using sequential don't cares. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1473-1484 [Journal]
   
2. Yang Cai, Martin D. F. Wong
   Channel/switchbox definition for VLSI building-block layout. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1485-1493 [Journal]
   
3. Gopalakrishnan Vijayan, Ren-Song Tsay
   A new method for floor planning using topological constraint reduction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1494-1501 [Journal]
   
4. Chung-Kuan Cheng, Yen-Chuen A. Wei
   An improved two-way partitioning algorithm with stable performance [VLSI]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1502-1511 [Journal]
   
5. A. R. Boothroyd, Stan W. Tarasewicz, Cezary Slaby
   MISNAN-a physically based continuous MOSFET model for CAD applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1512-1529 [Journal]
   
6. Yao-Tsung Tsai, Timothy A. Grotjohn
   Small-signal analysis of MESFET including the energy conservation equation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1530-1533 [Journal]
   
7. Gyo-Young Jin, Young-June Park, Hong-Shick Min
   Mixed particle Monte Carlo method for deep submicron semiconductor device simulator. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1534-1541 [Journal]
   
8. Srinivas Patil, Prithviraj Banerjee
   Performance trade-offs in a parallel test generation/fault simulation environment. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1542-1558 [Journal]
   
9. Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen
   Single-fault fault-collapsing analysis in sequential logic circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1559-1568 [Journal]
   
10. Doron Drusinsky-Yoresh
    A state assignment procedure for single-block implementation of state charts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1569-1576 [Journal]
    
11. Doron Drusinsky-Yoresh
    Decision problems for interacting finite state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1576-1579 [Journal]
    
12. Yie He, Guoxiang Cao
    A generalized Scharfetter-Gummel method to eliminate crosswind effects [semiconduction device modeling]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1579-1582 [Journal]
    
13. Yoshiyasu Takefuji, Kuo Chun Lee, Yong B. Cho
    Comments on 'O(n²) algorithms for graph planarization'. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1582-1583 [Journal]