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Publications of Author

1. Minshine Shih, Ernest S. Kuh, Ren-Song Tsay
   Performance-Driven System Partitioning on Multi-Chip Modules. [Citation Graph (0, 0)][DBLP]
   DAC, 1992, pp:53-56 [Conf]
   
2. Ren-Song Tsay, Jürgen Koehl
   An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement. [Citation Graph (0, 0)][DBLP]
   DAC, 1991, pp:620-625 [Conf]
   
3. Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu
   Proud: A Fast Sea-of-Gates Placement Algorithm. [Citation Graph (0, 0)][DBLP]
   DAC, 1988, pp:318-323 [Conf]
   
4. Ren-Song Tsay
   Exact Zero Skew. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1991, pp:336-339 [Conf]
   
5. Gopalakrishnan Vijayan, Ren-Song Tsay
   Floorplanning by Topological Constraint Reduction. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1990, pp:106-109 [Conf]
   
6. Ren-Song Tsay
   An exact zero-skew clock routing algorithm. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:242-249 [Journal]
   
7. Gopalakrishnan Vijayan, Ren-Song Tsay
   A new method for floor planning using topological constraint reduction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1494-1501 [Journal]
   
8. 
   Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model. [Citation Graph (, )][DBLP]
   
   
9. 
   Cycle count accurate memory modeling in system level design. [Citation Graph (, )][DBLP]
   
   
10. 
    Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation. [Citation Graph (, )][DBLP]
    
    
11. 
    An effective synchronization approach for fast and accurate multi-core instruction-set simulation. [Citation Graph (, )][DBLP]
    
    
12. 
    How to consider shorts and guarantee yield rate improvement for redundant wire insertion. [Citation Graph (, )][DBLP]
    
    
13. 
    Design optimization of a global/local tone mapping processor on arm SOC platform for real-time high dynamic range video. [Citation Graph (, )][DBLP]
    
    
14. 
    A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 mum technology. [Citation Graph (, )][DBLP]