Journals in DBLP

J. Low Power Electronics
2005, volume: 1, number: 1

1. Patrick Girard
   Welcome to the Journal of Low Power Electronics. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:1, pp:1-2 [Journal]
   
2. Christian Schuster, Christian Piguet, Jean-Luc Nagel, Pierre-André Farine
   An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:1, pp:3-10 [Journal]
   
3. Pilar Parra, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia
   Selective Clock-Gating for Low-Power Synchronous Counters. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:1, pp:11-19 [Journal]
   
4. Alin Razafindraibe, Michel Robert, Philippe Maurine
   Compact and Secured Primitives for the Design of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:1, pp:20-26 [Journal]
   
5. Kihwan Choi, Wei-Chung Cheng, Massoud Pedram
   Frame-Based Dynamic Voltage and Frequency Scaling for an MPEG Player. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:1, pp:27-43 [Journal]
   
6. Kihwan Choi, Kwanho Kim, Massoud Pedram
   Energy-Aware MPEG-4 FGS Streaming. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:1, pp:44-51 [Journal]
   
7. Hyung Gyu Lee, Naehyuck Chang
   Low-Energy Heterogeneous Non-Volatile Memory Systems for Mobile Systems. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:1, pp:52-62 [Journal]
   
8. Shalini Ghosh, Sugato Basu, Nur A. Touba
   Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:1, pp:63-72 [Journal]
   
9. Aurelia De Colle, Sanjay Ramnath, Mokhtar Hirech, Subramanian Chebiyam
   Power and Design for Test: A Design Automation Perspective. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2005, v:1, n:1, pp:73-84 [Journal]
   
10. Patrick Girard, Yannick Bonhomme
    Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:1, pp:85-95 [Journal]