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Title:
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Michel Robert: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. F. Gensolen, Guy Cathebras, Lionel Martin, Michel Robert
    An Image Sensor with Global Motion Estimation for Micro Camera Module. [Citation Graph (0, 0)][DBLP]
    ACIVS, 2005, pp:713-721 [Conf]
  2. Michel Robert, P. Gorria, Johel Mitéran, S. Turgis
    Design of a Real Time Geometric Classifier. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:656- [Conf]
  3. Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon
    Dynamic hardware multiplexing for coarse grain reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:270- [Conf]
  4. Pascal Benoit, Jürgen Becker, Michel Robert, Lionel Torres, Gilles Sassatelli, Gaston Cambon
    Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:703-706 [Conf]
  5. Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon, Didier Demigny
    A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:722-732 [Conf]
  6. Sébastien Pillement, Lionel Torres, Michel Robert, Gaston Cambon
    Concurrent Design of Hardware/Software Dedicated Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:410-414 [Conf]
  7. Michel Robert, Lionel Torres, Fernando Moraes, Daniel Auvergne
    Influence of Locig Block Layout Architecture on FPGA Performance. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:34-44 [Conf]
  8. Olivier Omedes, Michel Robert, Mohammed Ramdani
    A flexibility aware budgeting for hierarchical flow timing closure. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:261-266 [Conf]
  9. Camille Diou, Lionel Torres, Michel Robert
    A Wavelet Core for Video Processing. [Citation Graph (0, 0)][DBLP]
    ICIP, 2000, pp:- [Conf]
  10. Fernando Moraes, Michel Robert, Daniel Auvergne
    A Virtual CMOS Library Approach for East Layout Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:415-426 [Conf]
  11. S. Raimbault, Gilles Sassatelli, Gamille Cambon, Michel Robert, Sébastien Pillement, Lionel Torres
    Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:407-414 [Conf]
  12. Camille Diou, Lionel Torres, Michel Robert
    Implementation of a Wavelet Transform Architecture for Image Processing. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:101-112 [Conf]
  13. Gilles Sassatelli, Lionel Torres, Pascal Benoit, Gaston Cambon, Michel Robert, Jérôme Galy
    Dynamically Reconfigurable Architectures for Digital Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:63-74 [Conf]
  14. Augusto Gallegos, Philippe Silvestre, Michel Robert, Daniel Auvergne
    RF Interface Design Using Mixed-Mode Methodology. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:326-333 [Conf]
  15. Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon
    Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:176- [Conf]
  16. Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon
    Automatic Task Scheduling / Loop Unrolling using Dedicated RTR Controllers in Coarse Grain Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  17. Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon, Jürgen Becker
    Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:251-256 [Conf]
  18. Nicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert
    HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:21-28 [Conf]
  19. Michel Robert
    Increasing test coverage in a VLSI design course. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1135- [Conf]
  20. A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne
    Design Optimization with Automated Cell Generation. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:722-731 [Conf]
  21. A. Landrault, L. Pellier, A. Richard, C. Jay, Michel Robert, Daniel Auvergne
    Transistor Level Synthesis Dedicated to Fast I.P. Prototyping. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:156-166 [Conf]
  22. Alin Razafindraibe, Michel Robert, Philippe Maurine
    Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:634-644 [Conf]
  23. Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine
    A Method to Design Compact Dual-rail Asynchronous Primitives. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:571-580 [Conf]
  24. Christel-loic Tisse, Lionel Martin, Lionel Torres, Michel Robert
    Iris recognition system for person identification. [Citation Graph (0, 0)][DBLP]
    PRIS, 2002, pp:186-199 [Conf]
  25. Benoît Badrignans, Daniel Mesquita, Jean-Claude Bajard, Lionel Torres, Gilles Sassatelli, Michel Robert
    A Parallel and Secure Architecture for Asymmetric Cryptography. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:220-224 [Conf]
  26. Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Gilles Sassatelli, Gaston Cambon, Michel Robert, Fernando Moraes
    A new hardware countermeasure for masking power signatures of crypto cores. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:169-176 [Conf]
  27. Sébastien Pillement, Lionel Torres, Michel Robert, Gaston Cambon
    Fast Prototyping: A Case Study - The JPEG Compression Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:87-0 [Conf]
  28. Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon
    Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:128-137 [Conf]
  29. Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Gilles Sassatelli, Gaston Cambon, Michel Robert, Fernando Moraes
    Current mask generation: a transistor level security against DPA attacks. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:115-120 [Conf]
  30. Daniel Mesquita, Lionel Torres, Fernando Gehm Moraes, Gilles Sassatelli, Michel Robert
    Are coarse grain reconfigurable architectures suitable for cryptography? [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:276-281 [Conf]
  31. Lionel Torres, El-Bay Bourennane, Michel Robert, Michel Paindavoine
    A Recursive Digital Filter Implementation for Noisy and Blurred Images. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 1998, v:4, n:3, pp:181-191 [Journal]
  32. Denis Deschacht, Michel Robert, Nadine Azemard-Crestani, Daniel Auvergne
    Post-layout timing simulation of CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1170-1177 [Journal]
  33. Daniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert, Jean-Claude Bajard, Fernando Gehm Moraes
    A Leak Resistant Architecture Against Side Channel Attacks. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  34. Daniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert, Fernando Moraes
    A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPA. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  35. Alin Razafindraibe, Michel Robert, Philippe Maurine
    Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:340-351 [Conf]
  36. Nicolas Saint-Jean, Camille Jalier, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert
    HS Scale: A run-time adaptable MP-SoC architecture. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:39-46 [Conf]
  37. Nicolas Saint-Jean, Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert
    Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:88-95 [Conf]
  38. Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Michel Robert, Guy Cathebras, Gilles Sassatelli, Fernando Gehm Moraes
    Current Mask Generation: an Analog Circuit to Thwart DPA Attacks. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:317-330 [Conf]
  39. Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin
    Security evaluation of dual rail logic against DPA attacks. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:181-186 [Conf]
  40. Alin Razafindraibe, Michel Robert, Philippe Maurine
    Compact and Secured Primitives for the Design of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:1, pp:20-26 [Journal]

  41. Evaluation on FPGA of triple rail logic robustness against DPA and DEMA. [Citation Graph (, )][DBLP]


  42. Differential Power Analysis enhancement with statistical preprocessing. [Citation Graph (, )][DBLP]


  43. A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM. [Citation Graph (, )][DBLP]


  44. Delay modelling improvement for low voltage applications. [Citation Graph (, )][DBLP]


  45. Path runner: an accurate and fast timing analyser. [Citation Graph (, )][DBLP]


  46. Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs. [Citation Graph (, )][DBLP]


  47. Bio-inspiration helps computers: A new machine. [Citation Graph (, )][DBLP]


  48. The Perplexus Programming Framework: Combining Bio-inspiration and Agent-Oriented Programming for the Simulation of Large Scale Complex Systems. [Citation Graph (, )][DBLP]


  49. MPI-Based Adaptive Task Migration Support on the HS-Scale System. [Citation Graph (, )][DBLP]


  50. Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects. [Citation Graph (, )][DBLP]


  51. Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. [Citation Graph (, )][DBLP]


  52. Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. [Citation Graph (, )][DBLP]


  53. Evaluating the robustness of secure triple track logic through prototyping. [Citation Graph (, )][DBLP]


  54. Improvement of dual rail logic as a countermeasure against DPA. [Citation Graph (, )][DBLP]


  55. JubiTool: Unified design flow for the Perplexus SIMD hardware accelerator. [Citation Graph (, )][DBLP]


  56. BAF: A Bio-Inspired Agent Framework for Distributed Pervasive Applications. [Citation Graph (, )][DBLP]


  57. Triple Rail Logic Robustness against DPA. [Citation Graph (, )][DBLP]


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