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Raúl Jiménez: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia, Angel Barriga Barrios, Raúl Jiménez, José L. Huertas
    New CMOS VLSI linear self-timed architectures. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1995, pp:14-23 [Conf]
  2. José M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas
    Practical low-cost CPL implementations threshold logic functions. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:139-144 [Conf]
  3. Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia
    Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:316-326 [Conf]
  4. Raúl Jiménez, Antonio J. Acosta, Eduardo J. Peralías, Adoración Rueda
    An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:295-305 [Conf]
  5. Raúl Jiménez, Pilar Parra, Javier Castro, Manuel Sánchez, Antonio J. Acosta
    Optimization of Master-Slave Flip-Flops for High-Performance Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:439-449 [Conf]
  6. Raúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta
    A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:209-218 [Conf]
  7. Raúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta
    A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:491-500 [Conf]
  8. Francisco de Toro, Raúl Jiménez, Manuel Sánchez, Julio Ortega
    Synthesis of Hybrid CBL/CMOS Cell Using Multiobjective Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:629-637 [Conf]
  9. Fermín Dalmagro, Juan Jiménez, Raúl Jiménez, Haydée Lugo
    Bounded-rational-prisoners' dilemma: On critical phenomena of cooperation. [Citation Graph (0, 0)][DBLP]
    Applied Mathematics and Computation, 2006, v:176, n:2, pp:462-469 [Journal]
  10. Pilar Parra, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia
    Selective Clock-Gating for Low-Power Synchronous Counters. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:1, pp:11-19 [Journal]

  11. Connectivity Properties of Mainline BitTorrent DHT Nodes. [Citation Graph (, )][DBLP]

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